Data processing memory system

Details Data processing memory system Data processing memory system

1999-09-13

2002-02-05

Lane, Jack A. (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S131000, C711S149000

Reexamination Certificate

active

06345335

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to a memory system for use with a Harvard architecture central processing unit.
2. Description of the Prior Art
Harvard central processing units include separate data and instruction paths to associated memories allowing data access operations and instruction access operations to be performed in parallel. This can increase processing performance.
In classical Harvard designs completely separate data memory systems and instruction memory systems are provided. An example of such a classical Harvard design would be a DSP system in which the DSP code was provided in a ROM and supplied via the instruction access side to the CPU with all the data being stored within separate RAM storage and supplied via the data access side.
The term Harvard has also come to denote systems having separate data and instruction caches as the first level memory system, but with a single higher order memory system such as RAM or non-volatile storage.
Whilst a Harvard architecture has the advantage of allowing parallel access operations on the data and instruction sides, there are a number of disadvantages. Slow and complex mechanisms may need to be provided if data such as in-line constants is accessed from the instruction side, i.e. “literal” data that is part of the instruction memory image. In cases where the data and instructions share a common higher order address space, then there is the problem of ensuring “coherency” between the data words and instruction words. A further problem is that the instruction side is usually read-only and accordingly additional complexity and circuit elements need to be provided to support some debugging of operations, such as the insertion of break points within the instruction code.
A further disadvantage of existing Harvard systems is that at least the first level memory storage has to be divided between the data and instruction sides in a fixed manner when the hardware is provided. This fixed division will in many cases not make the best use of the total memory storage capacity being provided. For some applications, and at some times during execution, data side storage may be in short supply whilst there is an excess of instruction side storage. The converse situation may arise in other circumstances.
SUMMARY OF THE INVENTION
Viewed from one aspect the invention provides data processing apparatus comprising:
(i) a central processing unit having separately provided a data address bus, a data word bus, an instruction address bus and an instruction word bus;
(ii) a first level memory coupled to said central processing unit such that access to data words is via said data address bus and said data word bus and access to instruction words is via said instruction address bus and said instruction word bus; wherein
(iii) said first level memory has a data access port linked to said data address bus and said data word bus and an instruction access port linked to said instruction address bus and said instruction word bus such that a memory location within said first level memory may be access via both said data access port and said instruction access port.
The present invention addresses the above problems by providing a Harvard-type central processing unit having separate data and instruction sides with a common first level memory having both a data access port and an instruction access port. The separate data access port and instruction access port to the first level memory allows the parallel access operations on the data side and the instruction side to continue and so does not detract from the performance advantages associated with such Harvard-type systems. Providing the first level memory as a common structure allows high speed access to “literals” from the instruction side to be made without requiring a relatively slow access to a higher level common memory structure. As the data and instructions are stored within a common first level memory, there is guaranteed coherence between the data and instructions. The provision of the instructions within the same first level memory as the data has the result that the instructions may be relatively easily modified during debug, such as by the insertion of break points.
The common first level memory structure also allows the best use to be made of the total storage capacity provided with it being possible for a programmer to divide up the first level memory between the instructions and the data as a matter of simple configuration and also possibly to enable this to change dynamically.
The use as first level memory of a dual port structure or a structure having more than two ports would normally be considered disadvantageous by those in the field as the extra access ports mean that the same total amount of memory storage will consume a greater surface area on an integrated circuit. For example, a system in accordance with one embodiment of the invention might include 10 kilobytes of dual port memory whereas a prior art system may have been provided with two 5 kilobyte blocks of single port memory for the instruction and data sides respectively. The 10 kilobytes of dual port memory might have an area 30% greater than would be occupied by the two blocks of 5 kilobyte memory. Such a penalty would normally be considered prohibitive within the integrated circuit design field. However, the present invention recognizes that the numerous advantages associated with such an arrangement as discussed above outweigh this disadvantage and accordingly the invention moves against the technical prejudice in the field.
The first level memory may be addressed in various different ways. However, the invention preferably includes a data address decoder and an instruction address decoder whether this be in the form of respective content addressable memories storing cache TAGs, the type of row and column address decoder associated with bulk RAM storage or some other form.
A preferred embodiment that yields many of the advantages discussed above is one in which the data side includes read/write access whilst the instruction side provides only read access. Read/write access is required on the data side to enable useful processing to be performed whilst the restriction to read access on the instruction side simplifies the instruction side implementation and does not introduce a significant penalty. This is particularly the case with the common first level memory of the invention as write access to instruction words can be gained relatively rapidly via the data side if required.
The first level memory is the memory closest to the central processing unit. It is possible that this may be bulk RAM main storage in some relatively low performance applications. However, in preferred embodiments the first level memory is a cache memory with higher order main memory being provided in addition. In this context the invention provides a Harvard-type central processing unit in combination with a dual port cache to yield the significant advantages discussed above.
The principle of the invention may be developed further in preferred embodiments by the provision of a line fill access port for the cache memory. In such embodiments, if a cache miss occurs, then the resultant line fill operation can be performed via the line fill access port with the possibility for other processing to continue using the other access ports. The advantages of this preferred embodiment depend upon how critical was the cache miss that occurred in halting the processing flow.
In such embodiments having a line fill access port and a data access port providing write access, preferred embodiments recognize the possibility for a conflict arising through simultaneous operations seeking to write to the same memory location via the two different access ports. The cache controller may be arranged to detect such simultaneous conflicting write requests and arbitrate between them, e.g. to allow the line fill to complete before the data write.
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