Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
1998-08-17
2001-01-30
Coleman, Eric (Department: 2783)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S230000
Reexamination Certificate
active
06182209
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a data processing device. A data processing device is described in the architectural overview of the Philips 80C51XA processor, published in the “1996 Data handbook” IC25 published by Philips Semiconductors, pages 33 to 56.
It is desirable to minimize the amount of memory space needed for storing the instructions from a program for such a processing device. A reduction of the amount of memory space can be realized by using an instruction set with instructions of various lengths, e.g. 8, 16 or 24 bits, the most frequently occurring instructions being coded with the shortest length.
SUMMARY OF THE INVENTION
It is an object of the invention to provide for a data processing device in which the amount of memory space needed for storing instructions can be further reduced.
The invention provides for a data processing device according to claim
1
. By expressing the jump distance in terms of the number of instructions to be jumped over, instead of in terms of the number of memory addresses to be jumped over as in the prior art, a given range of relevant jump distances can be expressed with a smaller number of bits. For example, using a two bit coding, four different jump distances can be expressed using numbers of instructions, whereas using memory addresses this would require three bits on average, if one assumes an average of two addresses per instruction.
Instead of the length of the set of instructions (the number of addresses it occupies) that the device must jump over, the cardinal number of this set, i.e. the number of instructions in this set is specified in the instruction. Because the instruction set contains instructions of various lengths, e.g. some 8 bit long, some 12 bit long, some 16 bit long etc., the length of the set of instructions that the device must jump of over is not fixed. As a result, the address of the first instruction following the relative jump instruction that has to be executed can only be determined if the length of the set of intervening instructions is determined. For this reason, the instruction execution unit still reads the intervening instructions, but it does not execute these intervening instructions. Of course, this may make the execution of a relative jump instruction expressed in a number of instructions slower than that of a relative jump instructions expressed in a number of memory addresses (because in the latter case, the intervening instructions need not be read). However, it has been found that in typical programs many jumps jump over only a few instructions. For such jumps the loss of speed is very small. Moreover, a processing device which expresses jump distance in terms of memory addresses often will not realize its greater speed anyway because of disruption of pipelining caused by the jump instruction.
An embodiment of the data processing device according to the invention is an instruction execution pipeline with a decoding stage and an execution stage operating in parallel for successive instructions, disabling the execution stage following execution of the instance for a number of instruction execution cycles corresponding to the jump distance. In this way the jump instruction does not interrupt pipeline flow and no branch prediction is needed.
Another embodiment of the data processing device according to the invention is the relative jump instruction being a conditional relative jump instruction specifying a condition, the instruction execution unit excepts the set of instructions from execution when this condition is met, and the instruction execution unit executes the set of instructions when said condition is not met. This provides for conditional jump instructions.
Another embodiment of the data processing device according to the invention is the instruction execution unit interprets each possible contents of the field as expressing a respective number of instructions that is greater than zero. A jump of zero instructions is effectively no jump at all. Instruction space is saved, or alternatively the jump range is extended by not providing for the coding of jumps of zero instructions.
REFERENCES:
patent: 5008807 (1991-04-01), Krueger
patent: 5349391 (1994-09-01), Vlot
patent: 5367705 (1994-11-01), Sites
patent: 5434628 (1995-07-01), Spiero
patent: 5594733 (1997-01-01), Vlot
patent: 5613152 (1997-03-01), Van Meerbergen
patent: 5644699 (1997-07-01), Yoshida
patent: 5649145 (1997-07-01), Matsuo
patent: 5689507 (1997-11-01), Bloks
patent: 5787090 (1998-07-01), Van Niekerk
patent: 5812811 (1998-09-01), Dubey
patent: 5895500 (1999-04-01), Thomason
patent: 04037932 (1992-02-01), None
Philips Semiconductor Data Book, IC25, 1996; pp. 33-56.
Lippens Paul E. R.
Vlot Marnix C.
Coleman Eric
U.S. Philips Corporation
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