Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
Reexamination Certificate
1997-05-02
2001-08-07
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Combining two or more values to create address
C711S200000, C711S202000, C711S215000
Reexamination Certificate
active
06272615
ABSTRACT:
FIELD OF THE INVENTION
This invention relates in general to the field of electronic systems and more particularly to an improved modular audio data processing architecture and method of operation.
BACKGROUND OF THE INVENTION
Audio and video data compression for digital transmission of information will soon be used in large scale transmission systems for television and radio broadcasts as well as for encoding and playback of audio and video from such media as digital compact cassette and minidisc.
The Motion Pictures Expert Group (MPEG) has promulgated the MPEG audio and video standards for compression and decompression algorithms to be used in the digital transmission and receipt of audio and video broadcasts in ISO-11172 (hereinafter the “MPEG Standard”). The MPEG Standard provides for the efficient compression of data according to an established psychoacoustic model to enable real time transmission, decompression and broadcast of CD-quality sound and video images. The MPEG standard has gained wide acceptance in satellite broadcasting, CD-ROM publishing, and DAB. The MPEG Standard is useful in a variety of products including digital compact cassette decoders and encoders, and minidisc decoders and encoders, for example. In addition, other audio standards, such as the Dolby AC-3 standard, involve the encoding and decoding of audio and video data transmitted in digital format.
The AC-3 standard has been adopted for use on laser disc, digital video disk (DVD), the US ATV system, and some emerging digital cable systems. The two standards potentially have a large overlap of application areas.
Both of the standards are capable of carrying up to five full channels plus one bass channel, referred to as “5.1 channels,” of audio data and incorporate a number of variants including sampling frequencies, bit rates, speaker configurations, and a variety of control features. However, the standards differ in their bit allocation algorithms, transform length, control feature sets, and syntax formats.
Both of the compression standards are based on psycho-acoustics of the human perception system. The input digital audio signals are split into frequency subbands using an analysis filter bank. The subband filter outputs are then downsampled and quantized using dynamic bit allocation in such a way that the quantization noise is masked by the sound and remains imperceptible. These quantized and coded samples are then packed into audio frames that conform to the respective standard's formatting requirements. For a 5.1 channel system, high quality audio can be obtained for compression ratio in the range of 10:1.
The transmission of compressed digital data uses a data stream that may be received and processed at rates up to 15 megabits per second or higher. Prior systems that have been used to implement the MPEG decompression operation and other digital compression and decompression operations have required expensive digital signal processors and extensive support memory. Other architectures have involved large amounts of dedicated circuitry that are not easily adapted to new digital data compression or decompression applications.
An object of the present invention is provide an improved apparatus and methods of processing MPEG, AC-3 or other streams of data.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following figures and specification.
SUMMARY OF THE INVENTION
In general, and in a form of the present invention a data processing device for processing a stream of data is provided which has a central processing unit (CPU) with an instruction register for holding an instruction. The CPU is operable to process a data word in response to the instruction. An index register connected to the CPU is operable to provide a base address in response to the instruction. Address circuitry is connected to the CPU and is operable to form an address of the data word by combining a portion of the base address with a portion of an immediate field in the instruction.
In another form of the invention, decoder circuitry is connected to the address circuitry and selects a certain width for the base portion of the address in response to a field in the instruction.
In another form of the instruction, a method is provided for accessing multiple data structures in a data processing system using a common index value. The method first initializes an index register within the data processing system with the common index value. A first instruction is executed which has an indexed immediate addressing mode, wherein the first instruction has an immediate value comprising a first base value, such that a first data structure in a first portion of memory of the data processing system is accessed by the first instruction. A second instruction is executed which also has an indexed immediate addressing mode, wherein the second instruction has an immediate value comprising a second base value, such that a second data structure in a second portion of memory of the data processing system is accessed by the second instruction using the same index value as the first instruction.
In another form of the invention, a method is provided for performing multi-way branching in a data processing system. An index register is first initialized with a data value that is indicative of a target address in a group of instructions. A branch instruction having an indexed immediate addressing mode is executed that has an immediate field with a base value that points to the group of instructions. A specific target instruction is branched to by combining the base value and the target address.
Other embodiments of the present invention will be evident from the description and drawings.
REFERENCES:
patent: 3614741 (1971-10-01), McFarland
patent: 4388685 (1983-06-01), Kotok et al.
patent: 5357620 (1994-10-01), Suzuki
patent: 5509129 (1996-04-01), Guttag et al.
patent: 5809245 (1998-09-01), Zenda
MPEG-1, 3-11172.
MPEG-2, Information Technology—Generic Coding of Moving Pictures and Audio: AudioISO/IEC 13818-3, 2ndEdition, Feb. 20, 1997 (ISO/IEC JTC1/SC29/WG11 N1519), Int'l Org. for Standardisation Coding of Moving Pictures and Audio.
Digital Audio Compression Standard(AC-3), Dec. 20, 1995, Advanced Television Systems Committee, ATSC Standard.
TI-17424A (S.N. 08/475,251), allowed, Integrated Audio Decoder System and Method of Operation.
TI-17600 (S.N. 08/054,127), allowed, System Decoder Circuit With Temporary Bit Storage and Method of Operation.
TI-24442P (S.N. 60/030,106), filed Provisionally Nov. 1, 1996. Integrated Audio/Video Decoder Circuitry.
Gill Maria B. H.
Li Stephen (Hsiao Yi)
Ng Fuk Ho Pius
Rowlands Jonathan
Brady III W. James
Laws Gerald E.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Thai Tuan V.
LandOfFree
Data processing device with an indexed immediate addressing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data processing device with an indexed immediate addressing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing device with an indexed immediate addressing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2523434