Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
Patent
1996-01-11
1997-09-09
Harvey, Jack B.
Electrical computers and digital processing systems: memory
Address formation
Combining two or more values to create address
711214, 711202, G06F 720
Patent
active
056665105
ABSTRACT:
A CPU has an upper compatibility with a low-order CPU to expand a continuously usable address space relatively. For latching data information, registers are constructed for being an address register with a bit number larger than the address bit number of a low-order CPU. The data information has its byte/word size specified by the size bit of an operation code. The utilization of the data information of a long word size is specified by either the prefix code or the operation code to which is newly added the same bit number as that of the low-order CPU. For the data information of the byte size, the high-/low-orders of the byte size register to be utilized are specified by predetermined 1 bit of a register specifying field. For the data information of the word size, the high-/low-orders of the word size register are specified by the predetermined 1 bit of that data information.
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Hitachi Single-Chip Microcomputer H8/330, HD6473308, HD6433308 Hardware Manual, First Edition, Dec. 1989, pp. 25-77 and 340. (English Version of Item No. 1 Above).
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Baba Shiro
Hayakawa Yukihide
Hayashi Tsutomu
Mitsuishi Naoki
Nagayama Hiromi
Harvey Jack B.
Hitachi , Ltd.
Seto Jeffrey K.
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