Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-05-03
2002-11-12
Lefkowitz, Sumati (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S004000
Reexamination Certificate
active
06480920
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a data processing device and, more particularly, to a data processing device which has a plurality of function parts.
2. Description of the Related Art
A LAN card or a modem card is known as a card device which is attached to a personal computer so as to provide an additional function to the personal computer. The LAN card provides a LAN function to the personal computer. The modem card provides a modem function to the personal computer. Recently, a multi-function card device (PC card) which can provide a plurality of functions has become available on the market. The multi-function card device provides a plurality of functions by having a plurality of function parts each of which provides one of the functions. The multi-function card device includes a single state-machine part and an interface which connects the state machine to a bus provided in the personal computer.
The state-machine part manages each of the function parts in accordance with instruction provided through the bus. Japanese Laid-Open Patent Application No.7-334564 teaches such a state-machine part. However, the state-machine part cannot manage a plurality of function parts at the same time. That is, if an instruction with respect to one of the function parts is input when the state-machine part is being operated for a different one of the function parts, the state-machine part cannot accept the instruction.
The multi-function device may be provided with a bridge circuit which connects a plurality of buses having different specifications. That is, for example, the bridge circuit connects a Peripheral Component Interconnect (PCI) bus to a first card bus and a second card bus. In this case, the multi-function device (the bridge circuit) is provided with a single state-machine part which manages a first function part connected to the first card bus and a second function part connected to the second function bus. This state-machine part manages only one of the first function part and the second function part at a time. That is, the state-machine part cannot manage both the first function part and the second function part at the same time.
FIG. 1
is a time chart for explaining a data transferring operation performed by the above-mentioned conventional multi-function device. In the data transferring operation, data is transferred from a PCI bus to a card bus in accordance with a delayed transaction method.
In
FIG. 1
, PCLK is a clock signal, and PAD is data exchanged between the PCI bus side and the multi-function device. FRAME# represents a state of a signal line for notifying the multi-function device of the reception of address data (instruction) through the PCI bus. That is, when the signal line FRAME# is at a low level, this indicates that the address data is received through the PCI bus. IRDY# represents a state of a signal line for notifying the multi-function device of the completion of preparation for exchanging data with the PCI bus side from which the address data (instruction) is input. Additionally, DEVSEL# represents a state of a signal line which notifies the PCI bus side of the result of selection of one of the function parts corresponding to the address data (instruction). If the data to be transferred to the PCI bus side has not been prepared when the result of selection of the function part is notified, a signal line TRDY# is at a high level and a signal line STOP# is at a low level.
When the address data (A
1
) is input first time from the PCI bus, the data to be transferred to the PCI bus side is not prepared. Thereby, the signal line TRDY# is at the high level and the signal line STOP# is at the low level. At this time, preparation for the data (D
1
) to be transferred to the PCI bus is started. The preparation for the data (D
1
) by the function part is managed by the state-machine part. Since the operation of the state-machine part is solely directed to the management of the function part corresponding to the address data (A
1
), the state-machine part cannot manage any other function parts. Accordingly, if another address data (A
2
) is input from the PCI bus side, the address data (A
2
) cannot be accepted.
When the second address data (A
1
) is input after the preparation of the data (D
1
) to be transferred to the PCI bus side is completed, the signal line TRDY# is changed to the low level while the signal line STOP# is maintained to be at the high level. Thus, the data (D
1
) is transferred to the PCI bus side. Simultaneously, the state-machine part is released from the operation for managing the function part. Thereafter, if the address data (A
2
) is input again, the address data (A
2
) is accepted at this time, and the preparation for the data corresponding to the address data (A
2
) is started.
As mentioned above, the address data (A
2
) is not accepted if the address data (A
2
) is input when the state-machine part is being operated for managing one of the function parts. The operation for the address data (A
2
) can be performed when the address data (A
2
) is input after the preparation for the data (D
1
) corresponding to the address data (A
1
) is completed. Accordingly, there is a problem in that a plurality of function parts cannot be operated at the same time, and data transfer between the buses or within the multi-function device cannot be efficiently performed.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved and useful data processing device in which the above-mentioned problems are eliminated.
A more specific object of the present invention is to provide a data processing device in which a plurality of function parts can be operated at the same time so that data transfer between buses or within the device can be efficiently performed.
In order to achieve the above-mentioned objects, there is provided according to the present invention a data processing device adapted to be connected to a first bus, the data processing device comprising:
a plurality of function parts each of which provides a different function with respect to a signal input through the first bus; and
a plurality of state-machine parts connected to a respective one of the function units, each of the state-machine parts being operable independently.
According to the present invention, each of the state-machine parts is operable independently irrespective of whether other state-machine parts are being operated. That is, the plurality of state-machine parts can be operated at the same time. Thereby, the plurality of function devices managed by the respective state-machine parts can be operated at the same time. Thus, the first bus is prevented from being occupied by a single function part, which results in data transfer being efficiently performed.
Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5978858 (1999-11-01), Bonola et al.
patent: 7334564 (1995-12-01), None
Cooper & Dunham LLP
Lefkowitz Sumati
Ricoh & Company, Ltd.
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