Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-10-28
1998-10-27
Lall, Parshotam S.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711122, 711137, G06F 1208
Patent
active
058288600
ABSTRACT:
A data processing device includes a cache memory, a load buffer primary (LBP) for storing 1-line instruction data including an instruction requested to be transmitted by an instruction processing unit and transmitted from a main storage or a secondary cache memory, and a load buffer secondary (LBS) for storing 1-line instruction data preceded by the above described 1-line data. With this configuration, the device may determine the validity of prefetched data in the LBP using lower order bits of the addresses of the data. If the data are determined to be valid, the data stored in the LBS are stored in the cache memory. A cache storage device, hierarchically provided between a central processing unit a n d a main storage device, includes a cache memory, a storage buffer, a write-in buffer and a cache storage control unit. The cache storage device fast writes storage data into a write-in buffer instead of directly into cache memory. In the case of a miss in an access to a cache tag during the execution of a load command, move-in data are read out from the main storage device or a cache storage device of a different hierarchy, for storage into a write-in buffer. The data stored in the write-in buffer are then written into cache memory when the central processing unit executes another store command.
REFERENCES:
patent: 4737908 (1988-04-01), Shinohara et al.
patent: 4774654 (1988-09-01), Pomerene et al.
patent: 4851993 (1989-07-01), Chen et al.
patent: 5027270 (1991-06-01), Riordan et al.
patent: 5113515 (1992-05-01), Fite et al.
patent: 5146573 (1992-09-01), Sato et al.
patent: 5170476 (1992-12-01), Laakso et al.
patent: 5222223 (1993-06-01), Webb, Jr. et al.
patent: 5265212 (1993-11-01), Bruce, II
patent: 5317718 (1994-05-01), Jouppi
patent: 5371870 (1994-12-01), Goodwin et al.
patent: 5410653 (1995-04-01), Macon, Jr. et al.
German Official Action in Application No. P 43 35 444.5-53, mailed Dec. 16, 1997.
Miyaoku Hitoshi
Sasamori Koichi
Suga Atsuhiro
Yoshino Kazuhide
Fujitsu Limited
Lall Parshotam S.
Vu Viet
LandOfFree
Data processing device equipped with cache memory and a storage does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data processing device equipped with cache memory and a storage , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing device equipped with cache memory and a storage will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1621408