Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2007-02-27
2007-02-27
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
Reexamination Certificate
active
10663783
ABSTRACT:
A data processing device is disclosed. The device is provided with a plurality of data processing units; a first memory shared for storing data, to which each of the data processing units makes an access so as to perform an operation; a transfer completion time designation unit for designating a transfer completion time according to need, within which transferring the data in response to the accesses made by the data processing units should be completed; an expected transfer completion time calculation unit for calculating an expected transfer completion time needed for completing the data transfer in response to the accesses made by the data processing units, taking current access status of the first memory into consideration; and an access management unit for managing the access to the first memory based on the transfer completion time and the expected transfer completion time.
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English Translation of Summary of Office Action with respect to Japanese Patent No. 2002-272402.
Hattori Yasuhiro
Michiie Norio
Moteki Kiyotaka
Obata Yuriko
Okamura Takao
Doan Duc T
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Padmanabhan Mano
Ricoh & Company, Ltd.
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