Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2002-01-02
2004-08-03
Lane, Jack A. (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S103000, C711S165000
Reexamination Certificate
active
06772314
ABSTRACT:
Japanese Patent Application No. 2001-385, filed Jan. 5, 2001, is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a data processing device. More particularly, the present invention relates to a data processing device that can rewrite data stored in a non-volatile memory.
2. Prior Art
Conventionally, flash memories that store programs and data are mounted in data processing devices.
However, programs and data are present together in the same address space of a CPU (central processing unit) in a conventional data processing device. This makes it difficult to rewrite only data in the flash memory.
Also, there is another problem in that the program in the flash memory may be destroyed due to wrong operation of the CPU caused by, for example, program bugs, in cases other than the case when data in the flash memory is rewritten.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made in view of the problems described above, and it is an objective of the present invention to provide a highly reliable data processing device in which a ROM which stores a program rewriting a data storage region in a non-volatile memory is mapped in an address space of a CPU when the data storage region within the non-volatile memory such as a flash memory is rewritten, and the ROM is not mapped in the address space of the CPU in the other cases, whereby rewriting the data storage region in the non-volatile memory is facilitated, and the program storage region in the non-volatile memory is not rewritten due to wrong operation and the like in cases other than the case when the data storage region in the non-volatile memory is rewritten.
To solve the above problems, a data processing device in accordance with the present invention comprises:
a CPU (central processing unit);
a rewritable non-volatile memory including a program storage region that stores first and second programs to be executed by the CPU, and a data storage region that stores data to be accessed by the CPU;
a ROM (read only memory) that stores a third program to be executed by the CPU;
a RAM (random access memory) that is mapped in a first address range in an address space of the CPU; and
an address decoder which is equipped with a flag register, and maps the nonvolatile memory in a second address range in the address space of the CPU when the flag resister is in a first state and maps the ROM in the second address range in the address space of the CPU and maps the data storage region of the non-volatile memory in a third address range in the address space of the CPU when the flag resister is in a second state,
wherein the first program stored in the non-volatile memory includes a routine to transfer the second program stored in the non-volatile memory to the RAM, and to branch to a head address of the second program transferred to the RAM,
wherein the second program stored in the non-volatile memory includes a routine to set the flag resister of the address decoder to the second state, to call the third program stored in the ROM as a sub-routine, and to set the flag resister of the address decoder to the first state, and
wherein the third program stored in the ROM includes a routine to write data stored in the RAM in the data storage region of the non-volatile memory that is mapped to the third address range.
Here, the data processing device may be a single-chip microcomputer.
A ROM which stores a program rewriting a data storage region in a non-volatile memory is mapped in an address space of a CPU when the data storage region within the non-volatile memory such as a flash memory is rewritten, and the ROM is not mapped in the address space of the CPU in the other cases, whereby rewriting the data storage region in the non-volatile memory is facilitated, and the program storage region in the non-volatile memory is not rewritten due to wrong operation and the like in cases other than the case when the data storage region in the non-volatile memory is rewritten.
REFERENCES:
patent: 2001/0012975 (2001-08-01), Matsumoto
patent: 08-263281 (1996-10-01), None
patent: 10-247187 (1998-09-01), None
patent: 10-333898 (1998-12-01), None
Harness & Dickey & Pierce P.L.C.
Lane Jack A.
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