Data processing device

Details Data processing device Data processing device

1999-12-08

2003-11-11

Huynh, Kim (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S053000, C710S057000

Reexamination Certificate

active

06647442

ABSTRACT:

FIELD OF THE INVENTION
The present invention a concerns data processing device, particularly a data processing device that is used in a system that transmits and receives data packets by means of a serial bus that conforms to IEEE 1394 standards.
BACKGROUND OF THE INVENTION
In the past, in order to accept audio and video data, and control AV machines with a data processing device such as a personal computer, a separate video capture board, RS232C bus, etc. were required, and unified handling could not be done.
Thus, in recent years, standards suited to data transmission in the multimedia era have been proposed, for example, by means of “IEEE 1394 high-performance serial bus standards (hereinafter IEEE 1394 standards),” and environmental improvements have been made so as to be able to freely conduct high-speed, high-volume communication.
One example of a conventional data processing device is represented by reference numeral
101
in FIG.
4
. This data processing device
101
conforms to IEEE 1394 standards and is connected to a serial bus (hereinafter IEEE 1394 bus)
106
, via which the propagation of data packets is possible. A plurality of other data processing units are connected to this IEEE 1394 bus
106
. The data processing device
101
transmits request packets to these other data processing devices by means of said IEEE 1394 bus
106
and is designed to receive a series of response packets corresponding to the request packets formed in the other data processing devices to which the request packets have been transmitted.
The aforementioned data processing device
101
has a packet processing device
102
, a transmitting device
103
, a packet receiving device
104
, a transmitting buffer
105
, and a receiving buffer
107
. The transmitting device
103
is made up of a plurality of packet transmitting devices; here, three packet transmitting devices
103
1
-
103
3
.
The output of the packet processing device
102
is connected to the input of the transmitting buffer
105
, and the output of the transmitting buffer
105
is connected to the input of the transmitting device
103
, and the output of the transmitting device
103
is connected to the IEEE 1394 bus
106
.
In the data processing device
101
, in transmitting a request packet, first, the packet processing device
102
sequentially forms the request packets according to a prescribed program, and serially outputs them to the transmitting buffer
105
. The transmitting buffer
105
is designed as a FIFO (first in, first out) memory for temporarily storing the request packets that are sequentially formed by the packet processing device
102
.
Each packet transmitting device
103
1
-
103
3
of the transmitting device
103
successively reads the request packets that are stored in the transmitting buffer
105
one at a time and transmits them to the IEEE 1394 bus
106
.
When a request packet is sent to the IEEE 1394 bus
106
, the other data processing device that is specified by the contents of the request packets becomes the data processing device of the other party and sequentially receives the request packets from the IEEE 1394 bus
106
and reads their contents. The data processing device of the other party reads the data specified in response to the contents of the request packets from a memory region which it itself has, attaches prescribed information to the data that was read, forms sequential response packets corresponding to the request packets, and sequentially transmits them to the IEEE 1394 bus
106
.
The input of the packet receiving device
104
is connected to be IEEE 1394 bus
106
, the input of the receiving buffer
107
is connected to the output of the packet receiving device
104
, and the output of the receiving buffer
107
is connected to the input of the packet processing device
102
.
When a response packet reaches the packet receiving device
104
, the packet receiving device
104
determines whether the response packet is receivable as a function of the volume available in the receiving buffer
107
. Here, the term “receive” refers to the time that the response packet reaches the packet receiving device
104
until it is stored in the receiving buffer
107
.
Also, if there is space available in the receiving buffer
107
for storing a response packet, the packet receiving device
104
determines that it is possible to receive. The response packet is then output to the receiving buffer
107
via the IEEE 1394 bus
106
.
The receiving buffer
107
temporarily stores the response packet that has been input, and outputs it to the packet processing device
102
in response to the requests of the packet processing device
102
that were read. When the response packet is output to the packet processing device
102
, the region which that response packet had occupied is released.
The packet processing device
102
conducts such processes as storing the response packets that have been input to the prescribed memory devices.
When a response packet such as the one described above is received by the data processing device
101
, an acknowledgement indicating “success” is returned to the data processing device of the other party, and the fact that the response packet was received is communicated the acknowledgement is made up of 4 bits and indicates whether each transaction was completed.
In the above-mentioned data processing device
101
shown in
FIG. 4
, the packet transmitting devices
103
1
to
103
3
, after request packets are transmitted, enter a receive standby condition until response packets corresponding to those requests packets are received, and are designed not to transmit new request packets until the fact that a given response packet has been received is acknowledged at the packet receiving device
104
and communicated to each of the packet transmitting devices
103
1
to
103
3
.
Also, each packet transmitting device
103
1
-
103
3
is designed to be immediately return to a condition in which a new request packet can be transmitted after being released from the receive standby condition.
Thus, even if the empty volume of the receiving buffer
107
is small and the packet receiving device
104
cannot receive a response packet corresponding to a new request packet, there are cases when the packet transmitting devices (
103
1
to
103
3
) transmit as many new request packets as possible.
Thus, because a response packet cannot be received, if a response packet arrives, the data processing device
101
returns a “busy” acknowledgement to the data processing device of the other party.
When a “busy” acknowledgement is returned, the data processing device of the other party retransmits (reattempts) the response packet, and the reattempt is repeated until the packet receiving device
104
can receive the response packet and a “successful” acknowledgement is returned, and when a “successful” acknowledgement is not returned, the reattempt is repeated only a prescribed number of times. Since the IEEE 1394 bus
106
is used wastefully during this interval, the efficiency of the data exchange is greatly lowered.
In particular, when the data processing device
101
has a plurality of packet transmitting devices
103
1
to
103
3
as shown in
FIG. 4
, and the response packets corresponding to the plurality of request packets are transmitted at one time to the IEEE 1394 bus
106
, there were many instances when the sum of the data volumes of all of the response packets that were transmitted exceeded the available volume in the receiving buffer
107
, and there were frequently instances when the packet receiving device
104
could not receive all of these response packets at one time.
The present invention was designed for the purpose of solving the above-mentioned problems of the prior art, and its purpose is to offer technology which can increase the efficiency for the data exchange if the exchange, of data is conducted in a data processing device that is connected to an IEEE 1394 bus.
SUMMARY OF THE INVENTION
In order to solve the above-mentioned problems, the data processing device of one a

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