Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2001-01-04
2002-08-27
Yoo, DoHyun (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S202000, C711S205000
Reexamination Certificate
active
06442665
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing device, in particular, to a data processing device having a cache unit.
2. Description of the Related Art
Generally speaking, a data processing device such as a CPU in the related art has a cache memory built therein. Normally, a cache memory built in a CPU includes a primary cache, a store buffer and a reload buffer. Further, a secondary cache may be connected thereto externally.
For a CPU having such a cache memory built therein, a system, called a non-blocking cache, is employed for securing a bandwidth of accessing. The non-blocking cache system. is a system such that data can be bypassed to a CPU core from any of a primary cache, a store buffer and a reload buffer.
At this time, it is necessary to determine whether the primary cache, store buffer or reload buffer stores data required by the CPU core therein, and to select the data.
In the related art, when data is to be selected, all the bits of the virtual address provided from the CPU core are compared with all the bits of the virtual addresses or physical addresses of the primary cache, store buffer and reload buffer. Then, it is determined whether or not they coincide. Then, the data is provided from one, for which the bits coincide, to the CPU core.
However, in the related art, all the bits of the physical address of data are used for the comparison, and the data from the primary cache or store buffer is selected according to the result of the comparison. Accordingly, it is necessary to convert all the bits of the virtual address provided by the CPU core into a physical address. Therefore, a delay required for obtaining the required data is long, and, thereby, high-speed data processing in the device cannot be achieved.
SUMMARY OF THE INVENTION
The present invention has been devised in consideration of the above-mentioned matter, and an object of the present invention is to provide a data processing device by which it is possible to shorten a time required for obtaining the required data.
A data processing device according to the present invention, comprises:
a calculating part performing calculation;
a storing part storing data from the calculating part;
an address converting part converting an address, corresponding to requested data, provided by the calculating part;
a first comparing part comparing an address from the address converting part with an address in the storing part;
a second comparing part comparing the address, corresponding to the requested data, provided by the calculating part with an address in the storing part; and
a selecting part selecting the data stored in the storing part as that to be provided to the calculating part when the address comparison result of the first comparing part is coincidence and also the address comparison result of the second comparing part is coincidence.
Thereby, by combining the comparison result of the first comparing part with the comparison result of the second comparing part, it s possible to select the data stored in the storing part without performing strict address comparison. Thereby, it is not necessary to use all the bits of the address provided by the calculating part for comparison, and to provide the data to the calculating part at high speed.
Further, because it is possible to recognize from the comparison result of the second comparing part whether or not the requested data requested by the calculating part is stored in the storing part, it is possible to report to the calculating part whether or not the requested data is stored in the storing part instantaneously (because the second comparing part uses the address directly provided by the calculating part).
The calculating part may output a virtual address of data which it requests;
the address converting part may convert the virtual address from the calculating part into a physical address;
the first comparing part may compare the physical address from the address converting part with a physical address in the storing part; and
the second comparing part may compare part of the virtual address from the calculating part with part of a virtual address in the storing part.
Thereby, it is possible to perform bypassing of data from the cache (storing part) to the calculating part at high speed in a VIPT (Virtual Index Physical Tag) method.
The storing part may temporarily store a calculation result of the calculating part before it is stored in another storing part. Thus, the storing part acts as a so-called store buffer.
Thereby, it is possible to perform bypassing from the store buffer to the calculating part at high speed.
The storing part may temporarily store data from an external storage device such as a main storage device or a secondary cache, thus, act as a so-called reload buffer.
Thereby, it is possible to perform bypassing from the reload buffer to the calculating part at high speed.
Other objects and further features of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.
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patent: 5956752 (1999-09-01), Mathews
patent: 6138226 (2000-10-01), Yoshioka et al.
patent: 6157986 (2000-12-01), Witt
patent: 6360314 (2002-03-01), Webb, Jr. et al.
patent: 7-105094 (1995-04-01), None
patent: 8-6853 (1996-01-01), None
patent: 10-240618 (1998-09-01), None
Hataida Makoto
Muta Toshiyuki
Fujitsu Limited
McLean Kimberly
Staas & Halsey , LLP
Yoo Do-Hyun
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