Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2000-03-02
2002-06-18
Nguyen, Than (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S167000, C711S168000, C711S169000, C712S209000, C712S212000, C712S216000, C712S218000
Reexamination Certificate
active
06408372
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique to control a processing of data in a configuration where a plurality of data processings are performed concurrently and in parallel.
2. Description of the Background Art
When a CPU (Central Processing Unit) executes a program, generally, a series of operations combining a plurality of simple operations such as (1) fetch of an instruction, (2) decoding of the instruction and (3) execution of the instruction is repeated. For example, a data transfer processing is performed by repeating such a series of processings.
Now, a discussion will be made on a processing performed by a CPU inside a semiconductor memory device when the memory device receives data in a unit of sector from a host computer (hereinafter referred to as “host”).
FIG. 7
is a timing chart showing a case where operations or process steps ST
1
to ST
4
are executed on data D
1
and then the process steps ST
1
to ST
4
are executed on the next data D
2
. As shown in
FIG. 7
, the CPU in the memory device repeats a series of operations, i.e., (A) fetching data and storing it in a sector buffer inside the memory device (step ST
1
), (B) adding an error correcting code (ECC) to the received data (step ST
2
), (C) writing the data into a flash memory inside the memory device (step ST
3
) and (D) checking a write result (step ST
4
). The priorities of operations which the CPU executes are the steps ST
4
, ST
3
, ST
2
and ST
1
from higher to lower.
One of effective methods of executing a series of operations consisting of the steps ST
1
to ST
4
at higher speed is pipelining of the data processing. Specifically, respective circuits for the steps ST
1
to ST
4
are operated independently and in parallel, to improve operation efficiency. Such a pipelined processing is shown in a timing chart of FIG.
8
. As shown in
FIG. 8
, a circuit used for the data fetch operation ST
1
consecutively performs the operation ST
1
on a plurality of data D
1
to D
5
. As can be seen from comparison between
FIGS. 7 and 8
, this pipelined processing of
FIG. 8
can achieve a throughput twice and half as much as that of the processing of
FIG. 7
in the same time period from the time t
0
to the time t
8
.
While the data transfer processing is performed, the CPU always controls the states of the sector buffers used for the data transfer and the states of all the operations during execution. Specifically, the CPU checks whether or not each circuit completes its operation on data and is available for the operation on the next data, and if the circuit is available, the CPU makes the circuit perform the operation on the next data. Further, in the data fetch operation ST
1
, the CPU performs a control so as to avoid a wrong order of readout of data from the host.
A more specific discussion will be made on the pipelined data transfer processing and the above control of data processing by the CPU.
FIG. 9
is a schematic diagram of a conventional address space in a RAM (Random Access Memory)
12
P used by the CPU. As shown in
FIG. 9
, the RAM
12
P comprises a firmware processing region
13
P for storing instructions or programs (generally termed firmware (F/W)) needed to operate the CPU and an operation region
14
P (hereinafter referred to as “work buffer”) for controlling a pipelined processing.
The work buffer
14
P consists of the first to fourth work buffers
141
P to
144
P and the four work buffers
141
P to
144
P each store a current processing of predetermined data under execution. For example, at the time to in
FIG. 8
(see the state S
1
), the CPU controls the circuit for the operation ST
1
to execute the fetch operation ST
1
on the data D
1
while writing information indicating that the data D
1
is being subjected to the operation ST
1
into the first work buffer
141
P. After that, at the time t
1
(see the state S
2
), the CPU controls the circuit for the operation ST
2
to execute the ECC addition operation ST
2
on the data D
1
stored in the sector buffer while writing information indicating that the data D
1
is being subjected to the operation ST
2
into the first work buffer
141
P. On the other hand, at the same time t
1
, the CPU controls the circuit for the operation ST
1
to execute the fetch operation ST
1
on the data D
2
while writing information indicating that the data D
2
is being subjected to the operation ST
1
into the second work buffer
142
P, like the above-discussed state S
1
. Thus, the operations sequentially proceeds. The first work buffer
141
P, for example, is used as a work buffer only for the data D
1
until a series of operations ST
1
to ST
4
on the data D
1
are completed.
At this time, as conventional access methods when the CPU uses the work buffers
141
P to
144
P, (a) a method in which absolute addresses AD
141
P, AD
142
P, AD
143
P and AD
144
P of the work buffers
141
P,
142
P,
143
P and
144
P, respectively, are designated by firmware or in a program, (b) a method in which the address AD
141
P of the work buffer
141
P is used as a base address and the other work buffers
142
P,
143
P and
144
P are designated by offset addresses, and the like are used.
The above addresses AD
141
P, AD
142
P, AD
143
P and AD
144
P are mapped to addresses P
1
P, P
2
P, P
3
P and P
4
P, respectively, in the address space of the CPU, and the CPU accesses the addresses P
1
P, P
2
P, P
3
P and P
4
P to access the above addresses AD
141
P, AD
142
P, AD
143
P and AD
144
P.
When the CPU performs the above-discussed processing control, generally, the loading of the CPU, in other words, the processing time increases. As a result, the speed of data processing or the performance of data transfer is deteriorated. This tendency becomes more pronounced as the number of data to be pipeline-processed increases. Since the above data processing control is needed when a plurality of data processings are performed in parallel, it is strongly desired that the CPU operates with higher efficiency while performing such a processing control. One of measures to meet such a requirement is to improve an access of the CPU to the work buffers. Specifically, both the conventional access methods (a) and (b) have the following problem.
Discussing in detail, in both the access methods (a) and (b), the CPU has to control the correspondence between the data D
1
to D
5
and the first to fourth work buffers
141
P to
144
P. For example, in
FIG. 8
, the data to be subjected to the operation ST
4
to which the highest priority should be assigned by the CPU is changed from the data D
1
to the data D
2
when the state shifts from the state S
4
from the time t
3
till the time t
4
to the state S
5
from the time t
4
till the time t
5
. At that time, with the change of the data to be subjected to the operation ST
4
, the work buffer to be accessed by the CPU in executing the operation ST
4
is changed from the first work buffer
141
P to the second work buffer
142
P. Therefore, in both the conventional access methods (a) and (b), the CPU itself has to memory and control the addresses AD
141
P to AD
144
P of the work buffers to be accessed by the CPU in executing the operations ST
1
to ST
4
.
Further, when the state shifts from the state S
4
to the state S
5
, the first work buffer
141
P used only for the data D
1
is relieved (in an open state) and available to the next data D
5
. Specifically, the CPU always has to memory and control which one of the first to fourth work buffers
141
P to
144
P is available to the data fetch operation ST
1
.
Thus, in both the conventional access methods (a) and (b), the CPU has to control not only the data processing control but also the address of the work buffer to be accessed for the processing control and whether the work buffer is available or not.
One of control methods which could lighten the burden for controlling the address of the work buffer and whether available or not is as follows. Specifically, a possible method is to sequentially copy (move) the informations in the second to
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