Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2004-06-09
2009-02-03
Ellis, Kevin L (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S167000, C710S045000
Reexamination Certificate
active
07487300
ABSTRACT:
A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted. The time point at which the particular request is accepted is always within the validity duration interval in which the particular access request is made. The timing circuit varies the position of the acceptance time points within the validity duration intervals, so that the position is delayed to make room for previously accepting an access request from another processor. The position is subsequently moved back toward a start of the validity duration interval in successive steps during application of successive access requests from the first data processing circuit.
REFERENCES:
patent: 5202973 (1993-04-01), Ho et al.
patent: 5706482 (1998-01-01), Matsushima et al.
patent: 6412049 (2002-06-01), Pawlowski et al.
patent: 6775717 (2004-08-01), Tang et al.
patent: 6847650 (2005-01-01), Stone et al.
patent: 2002/0083287 (2002-06-01), Zumkehr et al.
patent: 2004/0003194 (2004-01-01), Bodas et al.
Implementing a 128Kx32 Dual-Port RAM Using the Flash370, Dec. 1995, Cypress Semiconductor Corporation, pp. 1-11.
Andrejic Ivan
Kessels Jozef Laurentius Wilhelmus
Ellis Kevin L
NXP B.V.
Rutz Jared I
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