Data processing circuit and method

Details Data processing circuit and method Data processing circuit and method

2008-07-15

2011-12-13

Chaudry, M. Mujtaba K (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S763000, C714S774000

Reexamination Certificate

active

08078947

ABSTRACT:
A data processing method is provided. Target page data are read from a memory cell array and addresses of multiple programmed-error bits are stored. A first syndrome polynomial and a second syndrome polynomial are obtained according to the target page data, and the target page data are saved as a first codeword and a second codeword. An errata locator polynomial is obtained according to the syndrome polynomials, and a first error count and a second error count are obtained according to the errata locator polynomial, the first codeword and the second codeword. A set of reference codes is obtained according to the errata locator polynomial. Read page data are outputted according to the addresses of the programmed-error bits, the first error count and the second error count. The read page data are corrected according to the set of reference codes to obtain corrected read page data.

REFERENCES:
patent: 4688207 (1987-08-01), Yoshimoto
patent: 2002/0108088 (2002-08-01), Kim
patent: 2007/0174755 (2007-07-01), Lee et al.

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