Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2001-06-19
2003-12-09
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S003000
Reexamination Certificate
active
06662261
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to a data processing arrangement that includes a plurality of processing circuits and a group of storage elements for the temporary storage of data intended for the processing circuits.
SUMMARY OF THE INVENTION
A data processing arrangement in accordance with the present invention can be used in, for example, a digital signal processor (DSP) which can carry out finite impulse response (FIR) filtering (FIR is an acronym for the phrase Finite Impulse Response) and can be implemented in the following manner. The group of storage elements forms a bank of registers to which each processing circuit has access. Each storage element (register) serves to store one data block. A data block is applied to a processing circuit by means of a selection circuit. This selection circuit selects a storage element on the basis of a control word. The data block stored in the selected storage element is applied to the relevant processing circuit.
It is an object of the invention to enable a cost reduction to be achieved.
According to the invention, a data processing arrangement as defined in the opening sentence has the following characteristic features. The arrangement comprises an element selection circuit for selecting a single storage element from a plurality of storage elements in order to apply the content of the selected storage element to an input of a processing circuit. The arrangement further comprises a group selection circuit for selecting a group of storage elements from a plurality of separate storage element groups in order to apply the contents of all the storage elements forming part of the selected group to an input of another processing circuit.
The invention takes the following aspects into consideration. There are applications in which a given type of data requires a certain processing while another type of data requires a different processing. The different data types need not necessarily be equal in size. An example of such an application is FIR filtering in accordance with the Global System for Mobile (GSM) telephony standard. In such an application the input data and the filter coefficient comprise 16 bits that are to be multiplied in order to obtain weighted input data. Adding up of the weighted input data produces terms of 32 bits or even 36 or 40 bits after addition.
In accordance with the prior art each storage element (register) is adapted to store one whole data block. Consequently, the largest data block will dictate the size of the storage elements. For example, the size of the storage elements will be 32 bits for an application as described above. A 16 bit input data block will then be stored in a 32 bit storage element. This also applies to a 16 bit filter coefficient. Consequently, a storage element containing an input data block or a filter coefficient will contain padding bits, for example zeros (0), to achieve filling out to 32 bits. As a result, the prior-art group of storage elements will not be utilized very efficiently in an application as described hereinbefore.
The following principle enables the group of storage elements to be used more efficiently. Certain storage elements are reserved for a certain type of data while the other storage elements are reserved for data of another type. In accordance with this principle, there will be two different sub-groups of storage elements in an application as described hereinbefore. There will be one sub-group of 16 bit storage elements for storing the input data and the filter coefficients. There will be another sub-group of 32 bit storage elements for storing the weighted input data and the running total thereof.
During data processing, it is possible that comparatively many data of a certain type and comparatively few data of another type are to be stored in a given time interval. The opposite may be the case in another time interval. This means that, if the principle described hereinbefore is applied, each sub-group of storage elements should include an adequate number of storage elements. Consequently, this will require a comparatively large number of storage elements, which is expensive, and these storage elements will not be used very efficiently.
In accordance with the invention, an element selection circuit enables a single storage element to be selected in order to supply the content of this storage element to an input of a processing circuit. A group selection circuit enables a group of storage elements to be selected from a plurality of separate groups of storage elements in order to supply the contents of all the storage elements forming part of the selected group to the input of another processing circuit.
Thus, the invention makes it possible to use a storage element for storing a data block of a small size as a whole, but also for storing a part of a large-size data block. In the last-mentioned case, the other parts of the data block will be stored in the other storage elements belonging to the same group. Thus, the invention enables any type of data to be stored in one or more storage elements without the use of padding bits. Consequently, the invention enables a flexible and efficient use of all the storage elements. As a result of this, the invention makes it possible to store data to be processed as well as the intermediate and final results by means of a comparatively small number of storage elements. The invention consequently enables a cost reduction to be achieved.
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Barnas Saida
Duboc Jean-Francois
Biren Steven R.
Gossage Glenn
Koninklijke Philips Electronics , N.V.
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