Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate
2000-11-15
2004-06-22
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing control for data transfer
Reexamination Certificate
active
06754809
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to data processing devices, electronic processing and control systems and methods of their manufacture and operation.
BACKGROUND OF THE INVENTION
Generally, a microprocessor is a circuit that combines the instruction-handling, arithmetic, and logical operations of a computer on a single semiconductor integrated circuit. Microprocessors can be grouped into two general classes, namely general-purpose microprocessors and special-purpose microprocessors. General-purpose microprocessors are designed to be programmable by the user to perform any of a wide range of tasks, and are therefore often used as the central processing unit (CPU) in equipment such as personal computers. Special-purpose microprocessors, in contrast, are designed to provide performance improvement for specific predetermined arithmetic and logical functions for which the user intends to use the microprocessor. By knowing the primary function of the microprocessor, the designer can structure the microprocessor architecture in such a manner that the performance of the specific function by the special-purpose microprocessor greatly exceeds the performance of the same function by a general-purpose microprocessor regardless of the program implemented by the user.
One such function that can be performed by a special-purpose microprocessor at a greatly improved rate is digital signal processing. Digital signal processing generally involves the representation, transmission, and manipulation of signals, using numerical techniques and a type of special-purpose microprocessor known as a digital signal processor (DSP). Digital signal processing typically requires the manipulation of large volumes of data, and a digital signal processor is optimized to efficiently perform the intensive computation and memory access operations associated with this data manipulation. For example, computations for performing Fast Fourier Transforms (FFTs) and for implementing digital filters consist to a large degree of repetitive operations such as multiply-and-add and multiple-bit-shift. DSPs can be specifically adapted for these repetitive functions, and provide a substantial performance improvement over general-purpose microprocessors in, for example, real-time applications such as image and speech processing.
DSPs are central to the operation of many of today's electronic products, such as high-speed modems, high-density disk drives, digital cellular phones, complex automotive systems, and video-conferencing equipment. DSPs will enable a wide variety of other digital systems in the future, such as video-phones, network processing, natural speech interfaces, and ultra-high speed modems. The demands placed upon DSPs in these and other applications continue to grow as consumers seek increased performance from their digital products, and as the convergence of the communications, computer and consumer industries creates completely new digital products.
Designers have succeeded in increasing the performance of DSPs, and microprocessors in general, by increasing clock speeds, by removing data processing bottlenecks in circuit architecture, by incorporating multiple execution units on a single processor circuit, and by developing optimizing compilers that schedule operations to be executed by the processor in an efficient manner. The increasing demands of technology and the marketplace make desirable even further structural and process improvements in processing devices, application systems and methods of operation and manufacture.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the invention, there is disclosed a data processing apparatus which uses a register file to provide a faster alternative to indirect memory addressing. The apparatus comprises a data register file comprising a plurality of registers, each of the plurality of registers accessed by a corresponding register number, at least one functional unit connected to the register file, at least one indirect register access instruction comprising an operand register number field and executable by the functional unit, and instruction decode circuitry connected to the register file and the functional unit. The instruction decode circuitry is responsive to the indirect register access instruction to recall data stored in an operand register specified by the operand register number in the instruction, identify the recalled data as a register access number, and recall operand data from a data register corresponding to the register access number for use as an operand by the functional unit. In further embodiments, only a limited set of registers can contain indirect register source operands, and only a limited set of instructions employ indirect register access. In another further embodiment, at least some indirectly accessible data registers are not directly accessible.
In accordance with another preferred embodiment of the invention, there is disclosed a data processing apparatus. The apparatus comprises a data register file comprising a plurality of registers, each of the plurality of registers accessed by a corresponding register number, at least one functional unit connected to the register file, at least one indirect register access instruction comprising a destination register number field and executable by the functional unit, and instruction decode circuitry connected to the register file and the functional unit. The instruction decode circuitry is responsive to the indirect register access instruction to recall data stored in a destination register specified by the destination register number in the instruction, identify the recalled data as a register access number, and store output data from the functional unit in a data register corresponding to the register access number.
An advantage of the inventive concepts is that the apparatus may more quickly execute table look up intensive algorithms, such as variable length decoding, than an apparatus employing only indirect memory addressing.
REFERENCES:
patent: 5809327 (1998-09-01), Wollan et al.
patent: 6178492 (2001-01-01), Matsuo
patent: 6588008 (2003-07-01), Heddes et al.
Balmer Keith
Guttag Karl M.
Hoyle David
Brady III W. James
Coleman Eric
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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