Data processing apparatus with a cache controlling device

Details Data processing apparatus with a cache controlling device Data processing apparatus with a cache controlling device

1997-10-20

2002-04-16

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S151000, C711S210000, C710S055000, C710S244000

Reexamination Certificate

active

06374334

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing apparatus with a cache memory (for example, a microprocessor), in particular, to a data processing apparatus with a cache controlling device that causes either of a data write request sent from a cache write buffer to a cache memory or a data read request sent from the cache memory to have precedence over the other, according to various conditions.
2. Description of the Related Art
FIG. 1
is a block diagram showing the configuration of a conventional cache block and a conventional CPU block. In
FIG. 1
, the cache block comprises a data cache storing device
1
, a data cache controlling device
2
that controls data input and data output to and from the data cache storing device
1
, and a cache write buffer
3
that temporarily stores data to be written to the data cache storing device
1
. The CPU block comprises an instruction controlling device
4
that outputs, for example, a load/store instruction to the data cache controlling device
2
, an arithmetic processing device
5
that performs various arithmetic operations, and a register file
6
that stores arithmetic operation data and so forth.
In
FIG. 1
, when the CPU block detects the load/store instruction, the CPU block causes the data cache controlling device
2
to execute the instruction. The arithmetic processing device
5
calculates a cache access address (data address). The cache access address is supplied to the data cache controlling device
2
and the data cache storing device
1
. When the load instruction is detected, after it is determined whether or not a cache hit takes place, the load data is output from the data cache storing device
1
to the register file
6
. When the store instruction is detected, store data is temporarily written from the register file
6
to the cache write buffer
3
. A data storage request is output from the cache write buffer
3
to the data cache controlling device
2
. In accordance with the data storage request the data cache controlling device
2
causes the data cache storing device
1
to store the swore data of the cache write buffer
3
.
FIG. 2
is an operation time chart showing the execution of the load instruction shown in FIG.
1
. In
FIG. 2
, when the data cache controlling device
2
receives the load instruction along with the data address at cycle T
1
, it accesses the cache memory at cycle T
2
. The data cache storing device
1
comprises a cache tag that stores a line address of the cache memory and a random access memory (RAM) portion. At cycle T
2
, both the cache tag and the RAM are accessed. At cycle T
3
, it is determined whether or not the read request data is stored in the cache (namely, a cache test takes place). When a cache hit is determined, the load data that is read from the cache memory is sent to the register file
6
.
FIG. 3
is an operation time chart of the store instruction shown in FIG.
1
. In
FIG. 3
, when the data cache controlling device
2
receives the store instruction along with the data address at cycle T
1
, as with the case of the load instruction shown in
FIG. 2
, the cache memory is accessed at cycle T
2
. At cycle T
3
, it is determined whether or not a cache hit takes place. When the store instruction is an instruction that causes data stored in the data cache storing device
1
to be rewritten, it is determined that a cache hit takes place. As shown in
FIG. 1
, the store data is stored in the cache write buffer
3
at cycle T
4
.
The store data stored in the cache write buffer
3
is stored in the data cache storing device
1
with precedence over, another instruction, for example, the load instruction. Alternatively, the store data is stored at a cycle at which another instruction such as the load instruction is not executed. In this case, the storage request of the store data that is output from the cache write buffer
3
is sent to the data cache controlling device
2
. Corresponding to the storage request, the data cache controlling device
2
causes the data cache storing device
1
to store the store data. Since data to be stored in the cache is stored in the cache write buffer
3
at cycle T
4
, the cache storage request is sent to the data cache controlling device
2
. When there is no instruction to be executed next, the storage data is stored in the data cache storing device
1
at cycle T
5
.
FIG. 4
is an operation time chart in the case that the data storage request that is sent from the cache write buffer
3
to the data cache storing device
1
corresponding to the store instruction shown in
FIG. 3
, and the load instruction that causes data to be read from the data cache controlling device
2
, contend. In
FIG. 4
, the operation will be described with an assumption that the store instruction has precedence over the load instruction. The, operations at cycles T
1
to T
3
of
FIG. 4
are the same as those of FIG.
3
. In
FIG. 4
, at cycle T
4
, the load instruction is supplied to the data cache controlling device
2
along with the data address.
In other words, at cycle T
4
, the cache storage request from the cache write buffer
3
and the load instruction contend. In this case, since the store instruction has precedence over the load instruction, the load instruction is not received at this cycle. Thus, data is stored from the cache write buffer
3
to the data cache storing device
1
. Consequently, the load instruction is not received until the next cycle (cycle T
5
). At cycle T
5
, an instruction response that represents that the load instruction can be received is sent to the instruction controlling device
4
. At cycle T
6
, the cache memory is accessed. At T
7
, when a cache hit is determined, the load data is output to the register file
6
.
FIG. 5
is an operation time chart in the case that the store instruction and the load instruction contend. In this case, the load instruction has precedence over the store instruction. The operations at cycles T
1
to T
3
shown in
FIG. 5
are the same as those shown in
FIG. 3
as with the case shown in FIG.
4
. At cycle T
4
, the load instruction and the data address are supplied to the data cache controlling device
2
. Thus, the load instruction and the cache storage request contend. In this case, the load instruction has precedence over the cache storage request. Thus, at cycle T
4
, the instruction response is sent to the instruction controlling device
4
. At cycle T
5
, the cache memory is accessed. At cycle T
6
, a cache hit is determined. The load data is output to the register file
6
. The cache storage request sent from the cache write buffer
3
at cycle T
4
is received by the data cache controlling device
2
at cycle T
5
. Thus, a cache storage response is output. At cycle T
6
, the store data is stored in RAM of the data cache storing device
1
.
As described in
FIG. 5
, if the load instruction has precedence over the other instruction, after the load instruction is received and the signal level of the instruction response to the load instruction becomes “L”, the store data is sent from the cache write buffer to the data cache storing device. If the load instruction is cancelled, the store data cannot be sent from the cache write buffer to the data cache storing device.
FIG. 6
is a time chart for explaining such a problem. In
FIG. 6
, as with the case shown in
FIG. 5
, the load instruction and the cache storage request contend at cycle T
4
. When the load instruction has precedence over the other instruction, the store data is not stored in the cache memory at cycle T
4
. At cycle T
5
, the load instruction cancellation signal is sent from the instruction controlling device
4
to the data cache controlling device
2
. This cancellation signal is sent from the instruction controlling device
4
to the data cache controlling device
2
in the case, for example, when the execution of an instruction of the CPU is stopped due to a particular cause. Next, the instruction cancellation signal will be described with reference to FIG.

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