Data processing apparatus that shares a single semiconductor...

Details Data processing apparatus that shares a single semiconductor... Data processing apparatus that shares a single semiconductor...

2007-08-07

2007-08-07

Kim, Hong (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S147000, C711S105000, C710S240000, C710S110000, C710S107000, C713S502000, C713S600000

Reexamination Certificate

active

10657464

ABSTRACT:
Multiple data processing circuits may share a semiconductor memory circuit, such as double-data-rate synchronous dynamic random access memory (DDR-SDRAM). A data processing circuit (202-1or202-2) ending control of a semiconductor memory circuit (201) supplies a clock enable signal and chip select signal at predetermined levels. A data processing circuit (202-2or202-1) starting control of a semiconductor memory circuit (201) supplies a clock enable signal and chip select signal at the same predetermined levels, before the data processing circuit (202-1or202-2) ending control stops supplying a clock enable signal and chip select signal. Therefore, a clock enable signal and chip select signal do not enter an undefined state, and malfunctions that could otherwise occur are prevented.

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