Data processing apparatus having DRAM incorporated therein

Details Data processing apparatus having DRAM incorporated therein Data processing apparatus having DRAM incorporated therein

1998-09-18

2001-09-25

Tung, Kee M. (Department: 2671)

Computer graphics processing and selective visual display system

Computer graphic processing system

Integrated circuit

C345S539000, C345S570000

Reexamination Certificate

active

06295074

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device in which a data processing device for performing an image processing and a memory device for storing image data or instructions are incorporated.
BACKGROUND ART
In recent years, personal computers have pushed into the field of work stations with intent to realize alternate for large-size computers by the network configuration of work stations. Also, an architecture for realizing a low-cost and high-speed graphic processing has recently been needed with the advance of home amusement equipments. In particular, a modified sprite processing for freely mapping source data of rectangles forms the basis of a three-dimensional graphics processing and is expected to have a drawing performance on the order of several ten thousands of polygons per second In order to realize more real display.
In order to improve the drawing performance of graphic LSI, a labor is taken for an improvement in the rate of data transfer between the graphic LSI and a frame buffer. A method for improving the data transfer rate includes (1) a method in which a high-speed interface is used and (2) a method in which a data bus width between the graphic LSI and the frame buffer is enlarged.
In the case of the method (1), the improvement in data transfer rate is realized using a DRAM provided with a high-speed page mode or a synchronous DRAM. The method using the synchronous DRAM is disclosed by JP-A-7-160249.
In the case of the method (2), the improvement in data transfer rate is realized by incorporating a frame buffer and a graphics controller in one chip with 128 bits or the like as the bit width of an internal bus. An example having a DRAM and a graphics controller incorporated in one chip is disclosed by “DEVELOPMENT OF GRAPHIC LSI HAVING FRAME BUFFER INCORPORATED THEREIN”, Nikkei Electronics, p. 17 (Apr. 10, 1995) and “ONE-CHIP IMPLEMENTATION WITH LOGIC—DRAM FORMS CORE OF SYSTEM”, Nikkei Microdevice, pp. 44-65 (March, 1996).
In the frame buffer incorporated graphic LSI disclosed by Nikkei Electronics, a portion of a 16-Mbit general purpose standard DRAM corresponding to 9 Mbits is removed and thereinstead replaced by a logic circuit including a controller. Regarding a DRAM incorporated graphic controller disclosed by Nikkei Microdevice, this reference has no specific disclosure excepting that the DRAM is incorporated.
DISCLOSURE OF INVENTION
However, in the case where the general purpose standard DRAM or the like is modified to incorporate the frame buffer in the graphic LSI as in the above-mentioned prior art, a restriction is imposed on the arrangement of a graphic controller since the mat construction of the memory, the input/output direction of data and so forth are determined by the specification of the general purpose standard DRAM. Also, unnecessary drawing-around of wiring is caused in order to provide an interface with the graphic controller.
Namely, in the case where the conventional general purpose standard DRAM or synchronous DRAM is incorporated as it is, it is difficult to obtain the optimum chip size. Also, since the graphic controller is filled in a vacant space of the DRAM, it becomes impossible to use a macro cell of the existing graphic controller as it is.
Further, the incorporation of the DRAM results in that a bus for making an access by the graphic controller to the DRAM does not appear on the external side. Accordingly, it becomes impossible to employ the conventional test method. Namely, in the case of the conventional separate-chip construction in which a graphic controller and an image memory such as a frame buffer are provided on separate chips, the direct detection from terminals of the image memory is possible upon physical fault of the connection terminals of the graphic controller and the image memories and even upon functional fault thereof. On the other hand, in the case of a one-chip construction in which a graphic controller and a image memory are provided on one chip, it will be impossible to directly monitor communication of information with terminals of the image memory.
An object of the present invention is to realize the optimum layout of a semiconductor integrated circuit device in which an image memory and an image processor are incorporated.
Another object of the present invention is to allow a semiconductor integrated circuit device with a logic and a memory incorporated therein to use the conventional test method for test of the memory as it is.
A further object of the present invention is to realize an incorporated image memory having an increased memory address depth and a capacity which is large when seen from an image processor.
A furthermore object of the present invention is to facilitate the control logic of a state machine of a logic of a semiconductor integrated circuit device in which the logic and a memory are incorporated.
The summary of typical ones of inventions disclosed by the present application will be mentioned in the following.
A a semiconductor integrated circuit device having an image memory and an image processor incorporated therein is arranged along the flow of information.
Also, a semiconductor integrated circuit device is provided with a test bus for an incorporated memory to allow the output to the exterior. Further, the incorporated memory is provided with a normal port and a test port.
Also, each of image memories incorporated in a semiconductor integrated circuit device is constructed by a plurality of identical memory modules each of which is allotted with the same row address.
Also, in the case where a logic incorporated in a semiconductor integrated circuit device makes an access to a memory, the latency of a memory read operation and that of a memory write operation are made equal to each other.


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Nikkei Electronics, Apr. 10, 1995, p. 17.
Nikkei Microdevices, Mar., 1996, pp. 46-65.

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