Electrical computers and digital data processing systems: input/ – Interrupt processing – Interrupt queuing
Reexamination Certificate
1998-10-08
2001-06-12
Niebling, John F. (Department: 2183)
Electrical computers and digital data processing systems: input/
Interrupt processing
Interrupt queuing
C712S244000
Reexamination Certificate
active
06247093
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a data processing apparatus that is capable of executing instructions either synchronously or asynchronously. More particularly, the invention relates to a data processing apparatus which allows either synchronous or asynchronous execution of instructions to be designated by a program, whereby the hardware may execute instructions either synchronously or asynchronously.
BACKGROUND OF THE INVENTION
In general, instructions are executed either synchronously or asynchronously. That is, hardware conventionally executes program instructions either in synchronism therewith or in an asynchronous fashion. However, a data processing system is disclosed in Japanese Patent Laid-Open No. Hei 6-4490 which executes instructions both synchronously and asynchronously. In manipulating messages, the disclosed system uses a SEND MESSAGE instruction that may be executed synchronously or asynchronously. Message manipulation is started and controlled by the SEND MESSAGE instruction and by information from a message manipulation block in main storage. The manipulation consists of executing the command designated in a message command block. Response information generated by the message manipulation is placed into a message response block in the main storage. An A bit (asynchronous bit) in the message manipulation block, designated by a program, causes a message sending function to be carried out either synchronously or asynchronously with respect to the SEND MESSAGE instruction. Specifically, the message sending function is executed in synchronism with the SEND MESSAGE instruction when the A bit is set to 0, and it is executed asynchronously if the A bit is set to 1. The SEND MESSAGE instruction designates one inter-system (I/S) subchannel for message manipulation involving the transfer of data, the message and a response between systems.
The execution of a message manipulation may involve a plurality of sending buffers paired with a plurality of receiving buffers. A typical setup for use with the paired buffers is disclosed in Japanese Patent Laid-Open No. Hei 6-85877 as “Data processing system having high-performance communication channels and operation recovery method for use with the same.”
A program may issue an asynchronous SEND MESSAGE instruction to an I/S subchannel (No.=a) of a message channel unit. In such a case, if the message channel unit is currently executing a SEND MESSAGE instruction on another I/S subchannel, the channel unit is busy with respect to the received asynchronous SEND MESSAGE instruction and does not execute the latter. Then the SEND MESSAGE instruction designated for the I/S subchannel (No.=a) in question is entered into a process queue within the system. Thereafter, the instruction is dequeued from the queue for reexecution. When an attempt is made to reexecute the SEND MESSAGE instruction on the targeted I/S subchannel (No.=a), the channel unit may still be executing another SEND MESSAGE instruction on another I/S subchannel. In that case, the SEND MESSAGE instruction is again placed into the process queue in the system. The steps are repeated until the SEND MESSAGE instruction in question is carried out. The concept involved in the above process is the same as that of asynchronous instructions for known I/O operations.
Unlike the asynchronous SEND MESSAGE instruction, a synchronous SEND MESSAGE instruction designated for one I/S subchannel cannot be executed by the message channel unit if the channel unit is carrying out another SEND MESSAGE instruction on another I/S subchannel. This is because the SEND MESSAGE instruction, synchronous in nature, cannot be placed into a process queue. In that case, the attempt to execute the instruction fails and the failure is reported to the program.
One message channel unit may be shared by a plurality of operating systems, as disclosed by Japanese Patent Laid-Open No. Hei 6-35725 in the form of “Method and system for sharing input/output resources.” When one operating system issues an instruction to such a shared message unit, another operating system may be already occupying the message channel unit. Thus, the possibility of the synchronous SEND MESSAGE instruction being unexecutable is even higher than otherwise. A failure to execute any synchronous SEND MESSAGE instruction requires suitable processing for recovery. The result is a lower level of system efficiency.
The data processing system disclosed in Japanese Patent Laid-Open No. Hei 6-4490 provides means for synchronously performing message handling in order to reduce the system overhead. The disclosed system is thus likely to encounter more cases of handling synchronous SEND MESSAGE instructions. As mentioned, the synchronous SEND MESSAGE instruction is more likely to be denied execution than the asynchronous SEND MESSAGE instruction.
The “data processing system having high-performance communication channels and operation recovery method for use with the same” disclosed in Japanese Patent Laid-Open No. Hei 6-85877 involve the use of a plurality of sending buffers in a message channel path unit. The sending buffers are paired with a plurality of receiving buffers located inside a structured external storage device. The sending-receiving buffer pairs correspond to a plurality of message manipulations. In this setup, one message channel unit is supposed to permit multiple message manipulations. However, since none of the pairs of sending and receiving buffers is assigned specifically to synchronous SEND MESSAGE instructions, if all buffer pairs happen to be busy, it is still impossible to execute any synchronous SEND MESSAGE instruction.
It is therefore an object of the present invention to reduce the probability that synchronous SEND MESSAGE instructions cannot be executed.
SUMMARY OF INVENTION
In carrying out the invention and according to one aspect thereof, there is provided a data processing apparatus which has hardware resources for executing instructions from a program synchronously and asynchronously and which allows either the synchronous or the asynchronous execution of instructions to be designated by an instruction from the program, the data processing apparatus comprising: queuing and executing means for entering an asynchronous instruction issued by the program into a queue and later executing the asynchronous instruction using the hardware resources at an appropriate time; notifying means for allowing the program to notify in advance the hardware resources of the execution of a synchronous instruction; and checking means for checking the status of notification in effect when an asynchronous instruction is to use the hardware resources.
In a preferred structure according to the invention, before issuing a synchronous instruction, the program is allowed to issue an instruction giving advance notice to the data processing apparatus of the intended use of the hardware resources. Given the notifying instruction, the apparatus reserves the hardware resources for executing the synchronous instruction in question. The reserved status is not canceled until the synchronous instruction has been executed. This boosts the probability of the synchronous instruction being executed.
REFERENCES:
patent: 5265257 (1993-11-01), Simcoe et al.
patent: 5301331 (1994-04-01), Ueno et al.
patent: 5386560 (1995-01-01), McCauley et al.
patent: 5410655 (1995-04-01), Greenfield et al.
patent: 5442802 (1995-08-01), Brent
Morikawa Takashi
Shigeno Takeshi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Niebling John F.
Whitmore S.
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