Electrical computers and digital data processing systems: input/ – Input/output data processing – Data transfer specifying
Reexamination Certificate
2002-11-22
2004-01-20
Perveen, Rehana (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Data transfer specifying
C710S005000, C710S018000, C710S019000, C710S033000, C710S038000, C709S217000, C711S145000
Reexamination Certificate
active
06681269
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing apparatus, a data processing system and a data transmitting method for communicating data to an external storage apparatus by using a serial interface, and to an external storage apparatus adaptable to the data processing apparatus, the data processing system and the data transmitting method.
2. Related Background Art
Hitherto, a data processing apparatus, to which a memory card including a storage medium, such as a flush memory, is connected, has been known. A conventional data processing apparatus of the foregoing type and a memory card arranged to be connected to the data processing apparatus will now be described with reference to the drawings.
As shown in
FIG. 1
, a data processing apparatus
100
includes a data processing block
101
, a register
102
, a host side serial interface circuit
103
and a host side controller
104
. The memory card
110
includes a memory
111
, a register
112
, a card side serial interface circuit
113
and a card side controller
114
.
The data processing block
101
of the data processing apparatus
100
reads data stored on the memory card
110
to subject read data to a variety of processes. Moreover, the data processing block
101
performs the variety of the data processes to generate data which will be written on the memory card
110
. That is, the data processing block
101
serves as a data processing circuit for a variety of apparatuses of a type which uses the memory card
110
.
The register
102
is a buffer between the data processing block
101
and the host side serial interface circuit
103
. That is, when data is supplied from the data processing block
101
to the host side serial interface circuit
103
, the data processing apparatus
100
temporarily stores data on the register
102
, and then supplies data to the host side serial interface circuit
103
. Similarly, the data processing apparatus
100
temporarily stores data in the register
102
, and then supplies data to the data processing block
101
when data is supplied from the host side serial interface circuit
103
to the data processing block
101
.
The host side serial interface circuit
103
converts data supplied from the data processing block
101
through the register
102
and a command supplied from the card side controller
114
into serial signals so as to supply the serial signals to the memory card
110
. Moreover, the host side serial interface circuit
103
converts data of the serial signal and the command supplied from the memory card
110
into parallel signals so as to supply the parallel signals to the data processing block
101
and the card side controller
114
.
The host side serial interface circuit
103
supplies a synchronizing signal (CLK) of data and the command and a chip-selection signal (CS) to the memory card
110
. The host side serial interface circuit
103
acquires a busy signal (BUSY) and an interrupt signal (INTERRUPT) supplied from the memory card
110
.
The host side controller
104
controls the data processing operation which is performed by the data processing block
101
and a data transmitting operation which is performed by the host side serial interface circuit
103
. The host side controller
104
supplies a command, which is a control command for the memory card
110
, to the memory card
110
through the register
112
.
On the other hand, the memory
111
of the memory card
110
includes, for example, a flush memory, on which data supplied from the data processing block
101
is stored.
The register
112
is a buffer between the memory
111
and the card side serial interface circuit
113
. That is, the memory card
110
temporarily stores data on the register
102
, and then supplies data, which must be written, to the memory
111
when data supplied from the data processing apparatus
100
is written on the memory
111
. Similarly, the memory card
110
temporarily stores data on the register
102
, and then supplies data, which must be read, to the card side serial interface circuit
113
when the data processing apparatus
100
reads data from the memory
111
. That is, the register
112
is a circuit having a function to serve as a page buffer for the flush memory.
The card side serial interface circuit
113
is controlled by the card side controller
114
in such a manner as to convert data of the parallel signal supplied from the memory
111
and the command supplied from the card side controller
114
into serial signals so as to supply the serial signals to the data processing apparatus
100
. The card side serial interface circuit
113
converts data of the serial signal and the command supplied from the data processing apparatus
100
into parallel signals so as to supply the parallel signals to the memory
111
and the card side controller
114
.
The card side serial interface circuit
113
acquires the synchronizing signal (CLK) of data and the command and the chip-selection signal (CS) from the data processing apparatus
100
. The card side serial interface circuit
113
supplies the busy signal (BUSY) and the interrupt signal (INTERRUPT) to the data processing apparatus
100
.
The card side controller
114
controls data storage, reading and erasing operations which are performed by the memory
111
in accordance with a command or the like supplied from the data processing apparatus
100
. The card side controller
114
controls the data transmitting operation which is performed by the card side serial interface circuit
113
. The host side controller
104
acquires, from the memory card
110
, the busy signal and the interrupt signal which serve as status signals for the memory card
110
.
An operation for transmitting data between the data processing apparatus
100
and the memory card
110
is performed through a transmission line arranged between the host side serial interface circuit
103
and the card side serial interface circuit
113
.
Between the card side serial interface circuit
113
of the data processing apparatus
100
and the card side serial interface circuit
113
of the memory card
110
, there are arranged five signal lines consisting of a CLK line, a CS line, a DT line, a BUSY line and an INT line.
The DT line is supplied with main data, that is, data processed by the data processing block
101
so as to be written on the memory
111
and data which must be written from the memory
111
so as to be supplied to the data processing block
101
. Moreover, a command which is supplied from the data processing apparatus
100
to the memory card
110
and which serves as a control command and a command which is supplied from the memory card
110
to the data processing apparatus
100
are transmitted to the DT line. That is, main data and the command formed into serial signals are bidirectionally transmitted to the DT line.
A synchronizing signal of main data and the commands which are transmitted to the DT line is supplied from the data processing apparatus
100
to the memory card
110
through the CLK line.
The so-called chip select signal is supplied from the data processing apparatus
100
to the memory card
110
through the CS line. In a period of time in which the level of the chip select signal is high, a fact is indicated that main data, the commands and the synchronizing signals are effective.
The busy signal indicating that the memory card
110
is performing a process is transmitted to the BUSY line. When the memory card
110
is performing, for example, a writing process and an access which is made from the data processing apparatus
100
is inhibited, the busy signal is supplied from the memory card
110
to the data processing apparatus
100
.
The interrupt signal indicating an interruption from the memory card
110
to the data processing apparatus
100
is supplied from the memory card
110
to the data processing apparatus
100
through the INT line.
The variety of the signals are transmitted through the above-mentioned transmitting lines in accordance with a
Hirabayashi Mitsuhiro
Nakanishi Kenichi
Frommer William S.
Frommer & Lawrence & Haug LLP
Perveen Rehana
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