Data processing apparatus configured to operate with one of...

Details Data processing apparatus configured to operate with one of... Data processing apparatus configured to operate with one of...

2006-10-24

2006-10-24

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S340000, C713S500000, C713S310000, C710S310000

Reexamination Certificate

active

07127626

ABSTRACT:
A data processing machine including a CPU which is configured to operate with an adjustable (variable) clock frequency. The clock frequency is adjusted in accordance with a clock change request signal. A plurality of clock change request signals have respective priority orders. A plurality of clock frequencies are prepared for the clock change request signals. When two or more clock change request signals are input, one of them is selected based on the priority order. The clock signal (clock frequency) to be applied to the CPU is changed in accordance with the selected clock change request signal. The data processing machine can adjust a timing for memory access to an optimal timing when the clock frequency is adjusted. The data processing machine can also deal with various clock frequency change requests.

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patent: 5832243 (1998-11-01), Seeman
patent: 6073244 (2000-06-01), Iwazaki
patent: 2001/0011356 (2001-08-01), Lee et al.
patent: 61-286913 (1986-12-01), None
patent: 7-287699 (1995-10-01), None
patent: 09-319651 (1997-12-01), None
patent: 2000-311027 (2000-11-01), None

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