Electrical computers and digital processing systems: support – Multiple computer communication using cryptography – Protection at a particular protocol layer
Reexamination Certificate
2001-10-04
2004-11-02
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Multiple computer communication using cryptography
Protection at a particular protocol layer
C713S400000, C713S500000, C713S502000
Reexamination Certificate
active
06813713
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing apparatus which is capable of executing a variety of operations as well as dealing with illegal external inputs in an operative state, and temporarily stopping components associated with the operations to prevent useless power consumption in a stopped state.
2. Description of the Related Art
At present, data processing circuits for executing a variety of data processing, referred to as ALU (Arithmetic and Logical Unit) and so on, have been used in practice and utilized in a variety of fields. Since such a data processing circuit executes data processing in synchronization with a clock signal, a data processing apparatus containing the data processing circuit typically contains a clock generator circuit as well.
However, there are portable data processing apparatuses which are mounted on a data processing terminal station and operated integrally therewith. In some cases, such portable data processing apparatuses do not internally generate a clock signal but are supplied with a clock signal from associated data processing terminal stations. Also, since portable data processing apparatuses generally use a battery as a power source, some of them stop useless data processing to save power consumption.
A prior art example of such data processing apparatus will be described below with reference to FIG.
1
. First, a data processing apparatus
100
illustrated herein as a prior art example comprises ALU
101
as a data processing circuit which is connected to bus line
102
.
Connected to bus line
102
are program memory
103
, data memory
104
, general register
105
, a plurality of I/Os (Input/Output)
106
, and soon. Program memory
103
is connected to program counter
107
and decoder
108
.
Decoder
108
is connected to standby controller
109
which functions as an operation control circuit. Standby controller
109
in turn is connected to INT (Interrupt)
110
and IAD (Illegal Access Detector)
111
which functions as an input monitor circuit.
Data processing apparatus
100
is formed as a portable type one which is mounted to a separated at a processing terminal station (not shown), and also has an external input terminal and a clock input terminal (not shown).
The external input terminal is connected to an external output terminal of the data processing terminal station to receive a variety of data and a variety of signals from the data processing terminal station, while the clock input terminal is connected to a clock output terminal of the data processing terminal station to receive a clock signal from the data processing terminal station.
Program memory
103
comprises, for example, EEPROM (Electrically Erasable Programmable Read Only Memory) or a flash memory, and stores an operation program comprised of a variety of instructions.
Program counter
107
is responsive to a variety of signals fed through the external input terminal from the outside, for example, to specify an address in program memory
103
at which an instruction to be executed is stored.
Decoder
108
reads an instruction from program memory
103
at an address specified by program counter
107
, and decodes this instruction to generate a variety of control signals which are then supplied to associated components such as ALU
101
.
ALU
101
executes a variety of data processing in synchronization with the clock signal fed through the clock input terminal from the outside corresponding to a variety of data fed through the external input terminal from the outside; a variety of data temporarily stored in data memory
104
; an operation program supplied thereto from program memory
103
through decoder
108
; and so on.
Data memory
104
, comprising, for example, RAM (Random Access Memory), temporarily stores data which is to be processed by ALU
101
. General register
105
, comprising a general-purpose register, temporarily holds a variety of data before processing, in the middle of processing, and after the processing.
I/Os
106
, which are peripheral circuits each having a variety of functions, is integrally controlled by ALU
101
. IAD
111
monitors a variety of data and a variety of signals fed from the outside, and executes predetermined counter-operations such as resetting of the entire apparatus, when it determines an external input as improper.
INT
110
receives an interrupt signal fed from the outside, an interrupt signal internally generated by any I/O
106
, and so on, and instructs ALU
101
or standby controller
109
to execute interrupt processing corresponding to a received interrupt signal.
Standby controller
109
temporarily stops the components such as IAD
111
, ALU
101
and I/Os
106
in response to a predetermined condition, for example, execution of a stop instruction, and so on, and restarts such temporarily stopped components in response to a predetermined condition such as an interrupt fed to INT
110
.
Data processing apparatus
100
configured as described above can be mounted to a separate data processing terminal station, and execute a variety of data processing in accordance with a variety of data and a clock signal supplied thereto from the data processing terminal station.
In this event, since program counter
107
specifies an address in program memory
103
in response to a variety of externally fed signals, an instruction at this specified address is read from program memory
103
and decoded to a control signal by decoder
108
.
Since this control signal is supplied to associated components such as ALU
101
, which, for example, executes a variety of data processing in synchronization with the clock signal fed through the clock input terminal from the external data processing terminal station in accordance with a variety of data fed through the external input terminal from the external data processing terminal station and an operation program supplied from program memory
103
through decoder
108
.
It should be noted that a variety of data and a variety of signals fed to data processing apparatus
100
from the outside as described above are monitored at all times by IAD
111
, so that if an illegal input, such as an input which does not comply with a standard, is detected by IAD
111
, IAD
111
resets the entire apparatus.
Also, in data processing apparatus
100
, a stop instruction in program memory
103
is decoded to a stop signal by decoder
108
in response to a predetermined condition, and this stop signal is supplied to standby controller
109
. Upon receipt of the stop signal, standby controller
109
temporarily stops the components such as IAD
111
, ALU
101
and I/Os
106
, there by making it possible to prevent useless power consumption in this stopped state.
Since INT
110
restarts temporarily stopped components in response to a predetermined condition such as an interrupt fed thereto even in a stopped state, this permits data processing apparatus
100
to restore a normal operative state.
Data processing apparatus
100
as described above can temporarily stop its components such as ALU
101
and IAD
111
to prevent useless power consumption, restore a normal operative state even from the stopped state, and deal with illegal external inputs by means of IAD
111
in the normal operative state.
However, since IAD
111
is also inoperative in a stopped state, data processing apparatus
100
cannot deal with illegal external inputs. To solve this problem, it is contemplated that IAD
111
is left operative at all times, in which case, however, IAD
111
consumes power even in a stopped state.
SUMMARY OF THE INVENTION
The present invention has been made in view of the problem as mentioned above, and its object is to provide at least one of a data processing apparatus and system which are capable of dealing with illegal external inputs without consuming power uselessly nothing in a stopped state.
In the data processing apparatus of the present invention, an operation program comprised of a variety of instructions is stored in a program memory, so t
NEC Electronics Corporation
Perveen Rehana
Scully Scott Murphy & Presser
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