Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
1999-12-22
2004-03-02
Ellis, Richard L. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S222000, C712S218000, C708S506000
Reexamination Certificate
active
06701427
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing apparatus and method for processing floating point instructions.
2. Description of the Prior Art
It is common for data processing apparatus to be required to perform various floating-point computations on data. It has been found that general purpose processors are not well suited to the performance of floating-point computations, and hence this has led to the development of specialised floating-point units (FPUs) to handle such computations.
If the operation to be performed by such an FPU can be broken down into a number of separate steps, it is common to provide a number of pipelined processing stages within the FPU. By such an approach, it is possible for a number of instructions to be executed simultaneously within the FPU. As an instruction is passed into the pipeline, the FPU will typically receive the operand data required for the instruction from a number of data registers, arid on completion of the instruction, will store the data result to a predetermined destination register.
In some situations, an instruction may have one or more operands that are specified by a result of one or more previous instructions already in the pipelined processing stages of the FPU. Such an instruction will be referred to hereafter as a dependent instruction. In such cases, it is clear that that dependent instruction cannot be executed until the result of each instruction upon which it depends is available, and this can impact on the processing speed of the FPU.
To alleviate this impact, it is known to direct (or “forward”) the result to the first pipelined stage at the same time as it is written to the destination register. This avoids the need to wait until the result has been written to the destination register and to then read the data from that register again before being able to execute the dependent instruction.
More recently, an approach has been taken in IBM's S/390 computer family where an unrounded result is forwarded back to the first stage of the pipeline along with a signal indicating whether rounding is required. This enables a further time saving, since the result data is forwarded before the final result is actually determined (i.e. before rounding has taken place), and hence less delay is incurred before execution of the dependent instruction can begin.
When executing instructions, it is possible that an exception condition may be detected by the FPU, and in such a situation it is often necessary to invoke an exception handling routine to deal with the exception, in order to ensure that an appropriate data result is placed in the destination register. Often, the presence of an exception will only become apparent when the final result is computed, and so often much of the exception determination logic is located in the final pipelined stages.
However, in such situations, the detection of an exception condition may occur later than required to stop the issue of subsequent instructions into the pipeline. Such instructions must be either completed or restarted. One known approach is to provide a significant area of memory, referred to as a state frame, in which all intermediate states in the pipeline can be stored as and when required. Thus, if an exception condition is detected, and hence the exception handling routine needs to be invoked to recover from the exception, then the state of all stages of the pipeline can be stored in the state frame, such that the pipeline can be restored to its previous state once the exception handling routine has completed the recovery process. Such an approach was employed in the Motorola MC68040 chip. This approach suffers from the drawback that an instruction, when exceptional, blocks completion of all subsequent instructions currently executing in the pipeline. Further, this technique requires significant time to process a store or load of a state frame to or from memory.
An alternative approach employed in prior art processing units involves the use of a history, or reorder, buffer. The reorder buffer typically stores the entire instruction stream of the data processing apparatus, and has logic arranged to send the instructions to the appropriate processing unit(s) of the data processing apparatus, and to subsequently place in the reorder buffer in association with the instruction the data result determined upon execution of that instruction. As each instruction reaches the bottom of the reorder buffer, it is “retired”, for example by storing the data result in the appropriate destination register. If, however, an exception condition is associated with the instruction being retired, then the exception handling routine is invoked to recover from the exception. Subsequent to the recovery process, the instruction stream is restarted from the instruction immediately following the retired instruction.
It will be appreciated by those skilled in the art that both of the above known approaches increase complexity, and hardware/memory requirements of the FPU, which hence increases the cost of the FPU.
Accordingly, an alternative approach to handling exceptions involves detecting exceptions pessimistically during an early pipelined stage, i.e. determining whether an exception may (as opposed to will) occur, and referring all such detected exceptions to the exception handling routine. Whilst this will involve detecting more exceptions than actually would occur, and incurring the processing overhead involved in bouncing such exceptions to the exception handling routine, this often in practice does not have a significant impact on processing speed in applications where exceptions will only occur very rarely. Further, the use of such pessimistic determination of exceptions dramatically reduces the amount of state that needs storing prior to handling the exception, since the instruction giving rise to the exception will not proceed to the next stage of the pipeline, and accordingly no further instructions will be issued. This in turn enables reductions in the size and cost of the FPU.
Assuming an FPU is to adopt the above mentioned pessimistic determination of exceptions, it would seem necessary for the exception determination logic to have the correct operands available when determining the presence of the exception. However, this would appear to preclude the potential speed benefits available by adopting the earlier described technique of forwarding an unfinalised result to the beginning of the pipeline to enable a dependent instruction to begin to be executed.
It is an object of the present invention to provide a data processing apparatus and method which enables efficient processing of dependent instructions when employing pessimistic exception determination techniques.
SUMMARY OF THE INVENTION
Viewed from a first aspect, the present invention provides a data processing apparatus for processing floating point instructions, comprising: an execution unit comprising a plurality of pipelined stages, and being responsive to a floating point instruction to apply a floating point operation to a number of operands to produce a final result, result data being generated during a predetermined pipelined stage with further processing then being performed on the result data in one or more subsequent pipelined stages to generate the final result; exception determination logic for determining based on the operands whether an exception may occur during application of the floating point operation to the operands, and to prevent the execution unit applying the floating point operation to those operands if it is determined that an exception may occur; a forwarding path for forwarding the result data generated in the predetermined pipelined stage during processing of a first floating point instruction to a previous pipelined stage for use as an operand of a second floating point instruction; control logic for generating predetermined control data related to the forwarded result data, the exception determination logic being arranged to use at least some of the
Hinds Christopher Neal
Rajagopal Arun Kumar Varadarajan
ARM Limited
Ellis Richard L.
Meonske Tonia L.
Nixon & Vanderhye P.C.
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