Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-04-12
2011-04-12
Elmore, Stephen C (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S147000, C711S154000, C711S156000
Reexamination Certificate
active
07925840
ABSTRACT:
The present invention provides a data processing apparatus and method for managing snoop operations. The data processing apparatus has a plurality of processing units for performing data processing operations requiring access to data in shared memory, with at least two of the processing units having a cache associated therewith for storing a subset of the data for access by that processing unit. A snoop-based cache coherency protocol is employed to ensure data accessed by each processing unit is up-to-date, and when an access request is issued the cache coherency protocol is referenced in order to determine whether a snoop process is required. Snoop control storage is provided which defines a plurality of snoop schemes, each snoop scheme defining a series of snoop phases to be performed to implement the snoop process, and each snoop phase requiring a snoop operation to be performed on either a single cache or multiple caches. When a snoop process is required, a snoop unit is used to reference the snoop control storage in order to identify, having regard to one or more properties of the access request, the snoop scheme to be employed to perform the snoop process. Such an approach provides a great deal of flexibility with regards to how snoop processes are implemented, in particular allowing different snoop schemes to be used dependent on the properties of the access request in question.
REFERENCES:
patent: 5860114 (1999-01-01), Sell
patent: 6438657 (2002-08-01), Gilda
patent: 2004/0186963 (2004-09-01), Dieffenderfer et al.
U.S. Appl. No. 11/454,834, filed Jun. 19, 2006, Mansell.
U.S. Appl. No. 11/709,279, filed Feb. 22, 2007;Ozer et al.
A. Moshovos et al, “JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers” Proceedngs of the 7thInternational Symposium on High-Performance Computer Architecture, Jan. 2001.
C. Saldanha et al, “Power Efficient Cache Coherence” Workshop on Memory Performance Issues in Conjunction with ISCA, Jun. 2001, pp. 1-15.
M. Ekman et al, “Evaluation of Snoop-Energy Reduction Techniques for Chip-Multiprocessors” Workshop on Duplicating, Deconstructing and Debunking, in Conjunction with ISCA, May 2002.
E. Atoofian et al, “A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors” IEEE International Parallel and Distributed Processing Symposium, 2007.
E. Bilir et al, “Multicast Snooping: A New Coherence Method Using a Multicast Address Network” Proceedings of the 26thAnnual International Symposium on Computer Architecture, May 1999.
M. Ekman et al, “TLB and Snoop Energy-Reduction using Virtual Caches in Low-Power Chip-Multiprocessors” ISPLED'02, Aug. 2002.
A. Moshovos, “RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence” Proceedings of the 32ndAnnual International Symposium on Computer Architecture, 2005.
Harris Antony John
Laycock Christopher William
Mathewson Bruce James
ARM Limited
Elmore Stephen C
Nixon & Vanderhye P.C.
LandOfFree
Data processing apparatus and method for managing snoop... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data processing apparatus and method for managing snoop..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing apparatus and method for managing snoop... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2729753