Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2001-10-25
2004-04-13
Huynh, Kim (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S071000, C370S509000, C370S512000
Reexamination Certificate
active
06721827
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing apparatus and a data processing method, for use in a high-speed serial communication.
2. Description of Related Art
One of world standards for optical transmission networks realizable of high-speed data communications is a SDH (Synchronous Digital Hierarchy). According to the SDH, a synchronous transfer module called a STM is provided as a data multiplexing unit. A STM-1 (Synchronous Transfer Module Level One) is a standard of the STM, and a bit rate of the STM-1 is 155.52 Mb/s.
The STM-1 has a frame consisting of a two-dimensional byte array of 9 columns by 270 rows. Head array of 9 columns by 9 rows of the two-dimensional byte array is called a section overhead, which will be called SOH, in the following. Array of 9 columns by 261 rows following the SOH, is called a payload. The SOH is a control part storing a frame synchronous signal, a maintenance information or the like, added to the payload, therein. The payload is a part storing multiplexed actual data therein.
According to the STM, because one frame is transmitted for every 125 microseconds, a bit rate is determined according as how many bytes one column by one row of data consists of. For example, according to the STM-1, because one column by one row of data consists of one byte, the bit rata is determined on 155.52 Mbps on the basis of the equation; 9 (columns)×270 (bytes)×(1/125 microseconds)=155.52. In the SDH, a STM-4 having four times as high a bit rata as the STM-1, wherein one column by one row of data consists of four bytes, a STM-16 having sixteen times as high a bit rata as the STM-1, wherein one column by one row of data consists of sixteen bytes, and so on are standardized.
Further, according to the STM, one frame is further partitioned into a plurality of time slots, for example, channels. Therefore, original data, that are user data or the like transmitted and received, are stored in each time slot, and thereby, a plurality of data are multiplexed. These multiplexed data are transmitted as serial data, through the SDH communication network.
In the data transmitted through the SDH communication network, predetermined data, for example, idle data, for indicating a data break or the like in the STM, are inserted. In order to distinguish the original data having the same code as a code of the idle data from the idle data, a predetermined data conversion is performed to the original data. Therefore, at the data receiving side, it is necessary to perform a transparent processing such that data converted at the data transmitting side is reconverted to the original data.
The transparent processing is a processing of parallel converting serial data received at the receiving side of the SDH communication network, to the parallel data, for every 8 bits, in order, and of converting (reconverting) the predetermined data that is transparent data converted at the transmitting side, of the parallel data, to the original data.
FIG. 12
is a schematic block diagram for showing a transparent processing according to an earlier development.
As shown in
FIG. 12
, serial data received at the data processing apparatus
100
are inputted to a transparent data detection unit
110
of the data processing apparatus
100
. Then, the transparent data detection unit
110
detects information on transparent data of the received serial data, for example, an address or the like of transparent data, and transmits the received serial data and the detected information on transparent data to a transparent data conversion unit
120
. The transparent data conversion unit
120
converts transparent data of the received serial data to predetermined original data on the basis of the detected information on transparent data.
When the transparent processing is carried out, and the transparent data are converted to the original data, the latter half byte of the detected transparent data is extracted from the detected transparent data. Thereby, idle data of bytes corresponding to the number of the transparent data are generated. Therefore, it is necessary to operate the data number that is the effective byte number, of one block that is one parallel data block, after the transparent data are converted, according to the data sequence, and to rearrange the effective data of the block on the basis of the effective byte number.
More specifically, in case the transparent processing is performed in the STM-16, when data are inputted for every four bytes at parallel to the transparent data detection unit, the transparent data detection unit detects transparent data in the inputted data. Then, the transparent data sampling unit samples the transparent data from the inputted data. Thereafter, the transparent data sampling unit moves data corresponding to the number of the transparent data sampled, forward, for every four bytes, and operates the effect byte number of the data sequence. The transparent data sampling unit outputs the data from which the transparent data have been sampled and the information on the effect byte number, to the transparent data array unit.
The transparent data array unit further moves the data to the part of the idle byte data, forward, on the basis of the data from which the transparent data have been sampled and the information on the effect byte number, to reconstruct the parallel data. Because the idle data stream occurs every when the data are moved forward, the data from which the transparent data are sampled, are shifted by a flip-flop (F/F), and a data is extracted from the shifted data to interpolate the idle data stream. In case the transparent processing is carried out to the data for every four bytes, in order to generate effect data for every four bytes, three shifted data is generated by the flip-flop (F/F), and the data is extracted from the three shifted data according to a selection signal.
On the other hand, with the increase of the communication data quantity, the utilization of a high-speed data communication on the basis of a STM-64 is increasing. Although a device drivable at 10 GHz is necessary for the high-speed data communication such as the STM-64, such a device does is not provided at present. As a result, considering the realization of the high-speed data communication by an existing FPGA (Field Programmable Gate Array), the data are processed for every 16 bytes at 78 MHz, at parallel.
However, because the transparent data sampling unit moves data of 16 byte parallel data, forward, there has been a problem that the transparent data sampling unit cannot processes the data at 78 MHz in the FPGA, by performing the same processing to the data as that to the 4 byte parallel data.
Further, in case the transparent data array unit rearranges the parallel data, in order to generate the effect data for every 16 byte parallel data, it is necessary that the F/F generates fifteen data and extracts the effect data from the fifteen generated data on the basis of the selection signal. Accordingly, there have been problems that the circuit scale is enlarged and the outputted selection signal becomes complex.
SUMMARY OF THE INVENTION
The present invention was developed in order to solve the problems as mentioned above.
An object of the present invention is to provide a data processing apparatus and a data processing method easily realizable of a transparent processing of a high-speed serial data on the basis of a STM or the like.
In accordance with a first aspect of the present invention, a data processing apparatus (for example, a data processing apparatus
1
shown in
FIG. 1
) for use in a high-speed serial data communication, comprises: a serial data conversion section (for example, an interface which is provided at an input terminal of the data processing apparatus
1
and which is not shown in figures) for receiving high-speed serial data, and converting the high-speed serial data to first predetermined set of parallel data; a transparent data information detection section (for example, a tran
Inoue Takao
Yamamoto Takehiro
Ando Electric Co. Ltd.
Huynh Kim
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