Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate
2000-04-28
2004-06-01
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing control for data transfer
C712S201000, C712S202000, C712S203000, C712S209000, C712S245000, C712S227000, C711S212000, C711S214000
Reexamination Certificate
active
06745320
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing apparatus such as microcomputer, microprocessor, data processor, CPU (Central Processing Unit), particularly to register architecture, upper compatibility and expansion of operational function, for example, a technology effective by applying to effective utilization of software resources, expansion of operational function and promotion of usability in a single chip microcomputer.
2. Description of the Related Art
According to a microcomputer in the form of a semiconductor integrated circuit, expansion of an address space, enlargement of an instruction set and high speed formation have been achieved. According to CPU (Central Processing Unit) of a microcomputer, its function is defined by softwares and accordingly, even in a microcomputer achieving expansion of an address space, enlargement of an instruction set and high speed formation, it is preferable to be able to effectively utilize software resources of an existing microcomputer.
Therefore, as an example of realizing the expansion of an address space and the enlargement of an instruction set while maintaining compatibility at an object level, there is provided a microcomputer disclosed in, for example, Japanese Patent Laid-Open No. 51981/1994. The publication discloses that it is effective for achieving expansion of an instruction set to adopt a load store architecture such as a so-to-speak RISC (Reduced Instruction Set Computer) architecture.
According to the load store architecture, an operational processing is executed by using general purpose registers of CPU. That is, there is not executed an operation directly using data on a memory, the data on the memory is temporarily transferred to the general purpose registers, the operation is executed on the transfer data and thereafter, a result of operation on the general purpose registers is rewritten to the memory. Therefore, when there is a general purpose register which is not used in the processing, the data on the memory may be transferred to the general purpose register. However, a number of the general purpose registers is limited and depending on a processing situation at inside of the microcomputer, there also is a case in which all of the general purpose registers are used. When all of the general purpose registers are used, in other words, when contents of all the general purpose registers must be held, before executing an operation with regard to data on the memory, after saving the contents of the general purpose registers to stack areas or the like, a required processing is executed and after finishing the processing, in order to restart an interrupted processing, the saved contents of the general purpose registers must be returned.
SUMMARY OF THE INVENTION
(Study Problem A)
As study problem A, the inventors have studied to increase general purpose registers of CPU while enabling to effectively utilize software resources by maintaining compatibility. Further, although matters concerning the study problem A are constituted by a content which has already been disclosed in the specification of Japanese Patent Application No. Hei 11-123450 which is a first Japanese basic application related to the present application, the content is not publicly known yet. A description will be given of the study problem A.
According to CPU adopting the load store architecture, data processing is executed centering on general purpose registers of CPU and accordingly, it is convenient that a number of the general purpose registers is large. Thereby, easiness or high speed formation of program can be achieved.
However, at which of general purpose registers the processing is executed, is generally designated by an instruction code and accordingly, it is necessary to hold a register designating field in correspondence with a number of the general purpose registers at inside of the instruction code. For example, 4 bits of the register designating field are needed for 16 of the general purpose registers. When the general purpose registers are intended to increase, the register designating field is increased. When the general purpose registers are increased to 64 which is 4 times as much as 16, 6 bits of the register designating field are needed. A processing object generally comprises data of 2 (source and destination) and therefore, a doubled bit number is needed in the register designating field.
When a basic unit of instruction is constituted by, for example, 16 bits (hereinafter, referred to as “word”), a rate of the bit number occupied by the register designating field is increased and as a result, a length of an instruction code is obliged to increase. Prolongation of the instruction code amounts to a reduction in the processing speed. The reason is that CPU executes operation after reading instruction and when a number of words (bit number) of instruction to be read becomes large, a number of reading the instruction per se is also increased. Further, enlargement of the register designating field is not compatible with existing instruction of existing CPU and compatibility with existing CPU becomes difficult to maintain.
As a technology of apparently increasing general purpose registers, there is provided a register bank system in which the general purpose registers are classified into groups referred to as bank and any of the banks are exclusively selected. Which bank is selected is designated by a control register or control instruction. Therefore, the instruction code is provided with only a register designating field in correspondence with the general purpose registers in the bank and the increase in the length of the instruction code can be restrained. However, there is needed an instruction for switching the register banks, further, in forming a program, which bank is to be selected must be conscious of and easiness of the program is liable to deteriorate. A number of the general purpose registers capable of being used at the same time is not increased and accordingly, when there is a task having a large amount of data and a task having a small amount of data, it is difficult to circulate each other allocation of the general purpose registers.
It is an object of the invention with regard to the study problem A to provide a data processing apparatus capable of increasing a number of general purpose registers while maintaining upper compatibility.
It is other object of the invention with regard to the study problem A to provide a data processing apparatus capable of increasing a number of general purpose registers without increasing overall instruction codes.
It is still other object of the invention with regard to the study problem A to provide a data processing apparatus capable of realizing easiness of program formation and promotion of processing function of CPU by increasing a number of general purpose registers while maintaining upper compatibility with regard to software resources.
(Study Problem B)
As study problem B, the inventors has studied capability of effectively utilizing software resources by maintaining compatibility with regard to an architecture of a load store type (achieving upper compatibility with regard to software resources) and capability of directly operating data on a memory while maintaining advantages of existing CPU such that a load store architecture or an RISC architecture is advantageous in improving operational speed. Further, although matters with regard to the study problem B have already been disclosed in the specification of Japanese Patent Application No. Hei 11-151890 which is a second Japanese basic application related to the present invention, the content has not been publicly known yet. A description will be given of the study problem B.
Advantages which seem to provide by making data on a memory directly operable are as follows.
When not only an operation is executed by loading data to a general purpose register but also the operation can be executed with regard to data on a memory without loading the data to the general purpos
Mattingly Stanger & Malur, P.C.
Pan Daniel H.
Renesas Technology Corp.
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