Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2001-05-03
2003-02-18
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S103000, C712S233000, C712S239000, C712S240000, C365S185330, C365S189011, C365S230010
Reexamination Certificate
active
06523084
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a data processing apparatus that is a semiconductor device such as a microcomputer and contains flash memory used in data processing.
BACKGROUND OF THE INVENTION
In the field of information processing by a computer system attached internally or externally to an office automation or industrial device, data processing is performed, for example, on data read and written between the device and the computer system, according to the intended use of the data, and data processing apparatuses for that data processing are widely used.
Today, such a data processing apparatus is used in the form of a semiconductor device such as a microcomputer or micro-controller and typically contains internal flash memory used for storing data during data processing.
The flash memory contained in such a conventional data processing apparatus will be described below.
FIG. 2
is a schematic diagram showing a structure of a NOR flash memory cell contained in a data processing apparatus. During a write into the flash memory cell, high potential HV
1
is applied to the gate (“G” in
FIG. 2
) of the memory cell, high potential HV
0
(HV
0
≠HV
1
) is applied to the drain (“D” in FIG.
2
), and the source (“S” in
FIG. 2
) is grounded so that some of electrons traveling from the drain to the source move to the floating gate (“FG” in
FIG. 2
) to write data in the cell, as shown in FIG.
2
A.
During a delete operation, the gate of the memory cell is grounded, high potential HV
2
is applied to the source, (where HV
2
is sufficiently lower than high potential HV
1
for the write operation, that is, HV
1
>HV
2
), and the drain is opened to discharge the electrons from the floating gate to delete the data, as shown in FIG.
2
C.
During a normal read operation, high potential HV
2
is applied to the gate of the memory cell (where HV
2
is sufficiently lower than high potential HV
1
for the write operation, that is, HV
2
>HV
2
), the source is grounded, and it is determined whether the potential of the drain is a High (H) level or Low (L) level to read data according to the level, as shown in FIG.
2
B.
The data processing apparatus having the conventional NOR flash memory configuration as describe above has the following problem: when the drain is at a high potential because of precharging or other reasons during normal read operation in the flash memory configuration, a phenomenon commonly called a “gate disturb” occurs in which, because the potential of the gate is at a high level even though it is sufficiently lower than the potential for the write operation, the cell becomes the same state as that for a write operation and electrons move into the floating gate little by little to change stored information, lowering the reliability of the data processing.
DISCLOSURE OF THE INVENTION
The present invention solves the above-described problem with the prior art and it is an object of the present invention to provide a data processing apparatus that allows the occurrence of a gate disturb effect to be reduced to improve the reliability of data processing using internal flash memory.
The data processing apparatus of the present invention is a data processing apparatus containing internal flash memory used for data processing by a CPU, the data processing apparatus comprising: a controller for controlling the operation of components during the data processing by the CPU; SRAM contained within the apparatus together with the flash memory; a selector for selecting an address information source for the SRAM; chip select R/W generation means for generating a chip select signal to the flash memory, a chip select signal and an R/W signal to the SRAM, and a control signal controlling the selection of the address information source by the selector, based on an execution address and the R/W signal indicating a read or write provided from the CPU and a signal indicating the start of a read or write provided from the controller; SRAM start address storage means for storing the start address of an available area in the SRAM; SRAM size storage means for storing the size of the available area in the SRAM; branch detection means for monitoring an execution address from the CPU to detect a branch process in the data processing and outputting a positive- or negative-direction branch signal depending on the branch direction of the branch process; SRAM address storage means for holding the address of the available area in the SRAM with the timing of the negative-direction branch signal from the branch detection means; END execution address storage means for holding an execution address from the CPU with the timing of the negative-direction branch signal from the branch detection means; START execution address storage means for holding an execution address from the CPU with the timing of a start execution address store instruction signal output from the controller; and SRAM address generation means for generating the address of the available area in the SRAM based on signals from the SRAM start address storage means, the SRAM address storage means, and the controller, wherein the chip select R/W generation means outputs the chip select signal to the flash memory, the chip select signal and R/W signal to the SRAM, and the control signal controlling the selection of the address information source by the selector so that a loop process section of a program stored in the flash memory resulting from a branch in the program is held in a storage area in the SRAM corresponding to a range from an address specified by the SRAM start address storage means to a value specified by the SRAM size storage means, based on the read start signal or write start signal output from the controller with the timing of the positive- or negative-direction branch signal from the branch detection means.
According to the above-described configuration, a loop process section of a program stored in the flash memory is held in a storage area in the SRAM that corresponds to a range from an address specified by the SRAM start address storage means to a value specified by the SRAM size storage means, thereby the section is read only from the SRAM when the loop process is performed the subsequent times. Thus, the flash memory is not accessed when the program is looped, and therefore the frequency of normal reads from the flash memory decreases to minimize the occurrence of the gate disturb effect, allowing the flash memory to hold data that is stable for an extended period of time.
As described above, a loop process section of a program stored in the flash memory is held in a storage area in the SRAM that corresponds to a range from an address specified by the SRAM start address storage means to a value specified by the SRAM size storage means, thereby the section is read only from the SRAM when the loop process is performed the subsequent times. Thus, the flash memory is not accessed when the program is looped, and therefore the frequency of normal reads from the flash memory decreases to minimize the occurrence of the gate disturb effect, allowing the flash memory to hold data that is stable for an extended period of time.
Thus, the occurrence of a gate disturb effect can be reduced and the reliability of data processing using the internal flash memory can be improved.
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patent: 5936971 (1999-08-01), Harari et al.
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patent: 6141700 (2000-10-01), Iwata
patent: 6230261 (2001-05-01), Henry et al.
patent: 6246634 (2001-06-01), Nojima
Dinh Ngoc V
Matsushita Electric - Industrial Co., Ltd.
Parkhurst & Wendel L.L.P.
Yoo Do Hyun
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