Electrical computers and digital processing systems: memory – Address formation
Reexamination Certificate
1998-05-27
2002-04-23
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
C710S057000
Reexamination Certificate
active
06378057
ABSTRACT:
BACKGROUND OF THE INVENTION
Description of the Related Art
As a data processing apparatus related to the present invention, there is a processor called a SVP (Serial Video Processor) described in Section 3.1 on Page 17 of the IEEE 1990 CUSTOM INTEGRATED CIRCUITS CONFERENCE. Composed of 1,024 processors integrated in a single chip, the SVP is a processor for carrying out real time digital processing on a video signal. The SVP has a SIMD (Single Instruction stream/Multiple Data stream) structure which allows pixel data on a horizontal scanning line to be processed concurrently. SIMD is the name of one of data processing methods adopted by a computer whereby data of different kinds is processed concurrently as if the data pertained to 1 job.
FIG. 1
is a block diagram showing a typical configuration of a conventional SIMD control parallel processor. As shown in the figure, the SIMD control parallel processor comprises a program control apparatus
1
, an input SAM (Serial Access Memory) unit
3
, a data memory unit
4
, a processing circuit unit
5
and an output SAM unit
6
.
The input SAM unit
3
, the data memory unit
4
, the processing circuit unit
5
and the output SAM unit
6
constitute a group of parallel element processors
2
arranged in a linear array. The element processors
2
are interlocked with each other under control in accordance with a program of the program control apparatus
1
. The program control apparatus
1
comprises a program memory for storing the program in advance and a sequence control circuit for carrying on the program. The program control apparatus
1
generates a variety of control signals in accordance with the program in order to control a variety of circuits.
It should be noted that the input SAM (Serial Access Memory) unit
3
, the data memory unit
4
, and the output SAM unit
6
are each implemented as a memory, detailed explanation of which is omitted. In an apparatus shown in
FIG. 3
, row address decoders for these memories are included in the program control apparatus
1
.
One element processor
2
is represented by a hatched block in
FIG. 1. A
plurality of element processors
2
are arranged in parallel, that is, in the horizontal direction of the figure. That is to say, the element processor
2
indicated by the hatch block comprises components of 1 processor.
Next, the operation of the linear array parallel processor for carrying out video processing shown in
FIG. 1
is explained.
Input data, strictly speaking, picture data of 1 pixel, is supplied to the input SAM unit
3
in accordance with a control signal output by the program control apparatus
1
. The element processors
2
from the leftmost one to the rightmost one shown in the figure sequentially process the data. That is to say, pieces of input data are supplied sequentially to input SAM cells of the input SAM unit
3
from the leftmost one to the rightmost one shown in the figure.
Since the number of element processors
2
is at least equal to the pixel count H in one horizontal scanning period of a video signal, pixel data of one horizontal scanning period of a video signal can be accumulated in the input SAM unit
3
. The operation to supply input data is repeated for each horizontal scanning period.
Each time data of 1 horizontal scanning period of a picture signal is accumulated in the input SAM unit
3
as described above, the program control apparatus
1
carries out processing by executing SIMD control on the input SAM unit
3
, the data memory unit
4
, the processing circuit unit
5
and the output SAM unit
6
in accordance with the program as described below. In addition, the SIMD control causes the following operations to be executed in all the element processors
2
concurrently in the same way.
The input data of 1 horizontal scanning period of a picture signal accumulated in the input SAM unit
3
is, if necessary, transferred from the input SAM unit
3
to the data memory unit
4
during the next horizontal scanning period to be used in the subsequent processing.
In a transfer of data from the input SAM unit
3
to the data memory unit
4
, the program control apparatus
1
makes an access to data of a predetermined bit count in the input SAM unit
3
selected by an input SAM read signal, and then outputs a memory access signal to write the data into a predetermined memory cell of the data memory unit
4
.
Next, the program control apparatus
1
supplies data stored in the data memory unit
4
of each element processor
2
to the processing circuit unit
5
of the element processor
2
in accordance with the program and lets the processing circuit unit
5
carry out arithmetic and logic processing on the data supplied thereto. Results of processing are then written at a predetermined address of the data memory unit
4
.
FIG. 2
is a block diagram showing a typical configuration of the processing circuit unit
5
. Pieces of data from the data memory unit
4
are supplied to a register
24
by way of a selector
20
, a register
25
by way of a selector
21
and a register
26
by way of a selector
22
. The selector
20
selects the value
1
set in advance, the piece of data output by the data memory unit
4
or data stored in the register
24
and outputs the selected one to the register
24
. A selector
21
selects the value
1
set in advance, the value
0
also set in advance or the piece of data output by the data memory unit
4
and outputs the selected one to a register
25
. By the same token, a selector
22
selects the value
1
set in advance, the value
0
also set in advance or the piece of data output by the data memory unit
4
and outputs the selected one to a register
26
. Signals generated by the program control apparatus
1
control how the selectors
20
,
21
and
22
select one of their 3 inputs. A register
27
is used for storing data representing a carry-over generated by a full adder
31
.
A logical product circuit
28
computes a logical product of the data stored in the register
24
and data stored in the register
25
. An exclusive logical sum circuit
29
computes an exclusive logical sum of data output by the logical product circuit
28
and data supplied by the program control apparatus
1
and supplies the exclusive logical sum to the full adder
31
. The full adder
31
also receives data stored in the register
26
and data stored in the register
27
. The full adder
31
computes the sum of these 3 inputs, outputting the sum and its carry-over to a selector
32
. The carry-over is also supplied to the register
27
by way of the selector
23
.
A selector
30
selects either the data output by the register
25
or data output by the register
26
and outputs the selected one to the selector
32
. The selector
32
selects 1 of 3 inputs: the data output by the selector
30
, the sum output by the full adder
31
and the carry-over also output by the full adder
31
and outputs the selected one to the data memory unit
4
. Signals generated by the program control apparatus
1
control how the selectors
30
and
32
select one of their inputs.
Assume that, for example, a signal generated by the program control apparatus
1
controls the selector
20
to let the selector
20
select the value
1
to be stored in the register
24
. In this case, since the logic value
1
is stored in the register
24
, data stored in the register
25
from the data memory unit
4
passes through the logical product circuit
28
as it is, entering the full adder
31
by way of the exclusive sum circuit
29
. The full adder
31
computes the sum of the data supplied from the register
25
by way of the exclusive logical circuit
29
, data stored in the register
26
from the data memory unit
4
and data representing a carry-over generated in previous processing and stored in the register
27
. The sum and a newly generated carry-over are output to the selector
32
. As described above, the carry-over is also supplied to the selector
27
by way of the selector
23
to be stored therein.
The program control apparatus
1
is also capable o
Frommer William S.
Frommer & Lawrence & Haug LLP
Kim Matthew
Simon Darren M.
Sony Corporation
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