Data processing and communicating system with high throughput pe

Details Data processing and communicating system with high throughput pe Data processing and communicating system with high throughput pe

1997-07-17

1999-09-28

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710128, G06F 1340

Patent

active

059580321

ABSTRACT:
A data communication system has a host bus connected to a central processing unit and a system memory, a peripheral component interconnect bus connected to a communication device equipped with a first state machine and a second state machine independently requesting a right to use the peripheral component interconnect bus and a bus bridge circuit connected between the host bus and the peripheral component interconnect bus and having a first-in-first-out memory for data read-out, and the bus first-in-first-out memory for data write-in and another bridge circuit assigns the right to use the peripheral component interconnect bus to the second state machine so as to transfer write-in data codes through the peripheral component interconnect bus to the first-in-first-out memory for data write-in until completion of a data transfer from the system memory through the host bus to the first-in-first-out memory for data read-out, thereby improving the throughput of the peripheral component interconnect bus.

REFERENCES:
patent: 5553310 (1996-09-01), Taylor et al.
patent: 5594882 (1997-01-01), Bell
patent: 5613075 (1997-03-01), Wade et al.
patent: 5768548 (1998-06-01), Young et al.
John P. Hayes "Computer Architecture and Oganization", pp. 409-417, 1978.

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