Data prefetching of a load target buffer for post-branch instruc

Details Data prefetching of a load target buffer for post-branch instruc Data prefetching of a load target buffer for post-branch instruc

1997-12-29

2000-02-22

Kim, Kenneth S.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711213, 712225, 712239, G06F 938

Patent

active

060292288

ABSTRACT:
A method of operating a microprocessor (12). The method first receives (64) a plurality of instructions arranged in a sequence from a first instruction through a last instruction. The method second identifies (66) a branch instruction as one of the plurality of instructions, wherein the branch instruction has a target instruction address. The method third determines two factors for the branch instruction, the first being a prediction value (72) indicating whether or not program flow should pass to the target instruction address, and the second being an accuracy measure (74, 76) indicating accuracy of past ones of the prediction value. The method fourth identifies a data fetching instruction following the branch instruction in the plurality of instructions. Lastly, the method issues a prefetch request (70, 78) for the data fetching instruction in response to the accuracy measure.

REFERENCES:
patent: 5377336 (1994-12-01), Eickemeyer et al.
patent: 5778435 (1998-07-01), Berenbaum et al.
patent: 5822790 (1998-10-01), Mehrotra
patent: 5928358 (1999-07-01), Takayama et al.

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