Data pre-fetch system and method for a cache memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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C711S118000

Reexamination Certificate

active

06993630

ABSTRACT:
A system and method for pre-fetching data signals is disclosed. According to one aspect of the invention, an Instruction Processor (IP) generates requests to access data signals within the cache. Predetermined ones of the requests are provided to pre-fetch control logic, which determines whether the data signals are available within the cache. If not, the data signals are retrieved from another memory within the data processing system, and are stored to the cache. According to one aspect, the rate at which pre-fetch requests are generated may be programmably selected to match the rate at which the associated requests to access the data signals are provided to the cache. In another embodiment, pre-fetch control logic receives information to generate pre-fetch requests using a dedicated interface coupling the pre-fetch control logic to the IP.

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patent: 6230241 (2001-05-01), McKenney
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patent: 6601153 (2003-07-01), Engelbrecht et al.
patent: 6631447 (2003-10-01), Morioka et al.
patent: 6681297 (2004-01-01), Chauvel et al.

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