Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-01-30
2007-01-30
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S795000, C714S796000, C375S262000, C375S341000
Reexamination Certificate
active
10664882
ABSTRACT:
In playback of data recorded on an optical disk, an error minimization circuit holds a plurality of ideal values for partial response (PR) equalization as equalization targets, and updates tap coefficients of a finite impulse response (FIR) filter so that the errors between the outputs of the FIR filter reflecting the output of an analog-to-digital converter (ADC) and the equalization targets are minimized. An error detection circuit and an addition/weighting circuit generate a signal representing the errors between the outputs of the FIR filter and the equalization targets as a parameter signal correlated with the error rate of played-back data. The quality of the analog signal is adjusted so that the parameter signal is minimized, to thereby optimize the margin of the error rate of played-back data.
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Aida Kazutoshi
Horibe Ryuusuke
Takahashi Toshihiko
Abraham Esaw
De'cady Albert
McDermott Will & Emery LLP
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