Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2011-01-18
2011-01-18
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S056000, C710S310000
Reexamination Certificate
active
07873761
ABSTRACT:
The present invention relates to a data pipeline management system and more particularly to a minimum memory solution for unidirectional data pipeline management in a situation where both the Producer and Consumer need asynchronous access to the pipeline, data is non-atomic, and only the last complete (and validated) received message is relevant and once a data read from/write to the pipeline is initiated, that data must be completely processed. The data pipeline management system according to the invention can be implemented as a circular queue of as little as three entries and an additional handshake mechanism, implemented as a set of indices that can fit in a minimum of six bits (2×2+2×1). Both the Producer and Consumer will have a 2 bit index indicating where they are in the queue, and a 1 bit binary value indicating a special situation. Both parties can read all the indices but can only write their own, i.e. P and wrapP for the Producer and C and wrapC for the Consumer. For management of the handshakes a set of rules is provided.
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Castanha Ricardo
Vermunt Franciscus Maria
Vos Tom
Dang Khanh
NXP B.V.
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