Data phase alignment circuitry

Details Data phase alignment circuitry Data phase alignment circuitry

1993-12-01

1996-04-16

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327152, H04L 700, H04L 2536, H04L 2540

Patent

active

055090370

ABSTRACT:
A data phase alignment circuit (34) is provided to align incoming plesiochronous data with a known clock phase. Multiple phases of a clock signal are provided to a data capture circuit (40), which captures the incoming plesiochronous data with at least one of the clock phases. A data transition decoder (44) then determines the time of data transition with respect to the multiple phases of the clock. The captured data is then realigned with a selected phase of the multiple clock phases by a data retimer circuit (50) and provided as the output (64). The resultant data is therefore aligned with a known phase of the clock signal and is no longer plesiochronous with respect to the clock signal. Data shifting due to data jitter, drift and wander may also be correct with a slip buffer (38).

REFERENCES:
patent: 4012598 (1977-03-01), Wiley
patent: 4860283 (1989-08-01), Takano et al.
patent: 5022056 (1991-06-01), Henderson et al.

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