Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-12-04
2007-12-04
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
11157181
ABSTRACT:
A data path optimization element is used in a behavioral synthesis process to optimize portions of an algorithmic description of a digital logic circuit. Directives are provided in the algorithmic description to identify subsets of the algorithmic description that can be extracted and optimized. The optimization includes identification of certain operators, function calls, conditional statements, or other relationships in the subset, and then compression of the extracted subset into or more data path components in a building block. The building block thus generated is substituted back into the algorithmic description and used in subsequent operations during the behavioral synthesis process, thereby leading to a more optimum design in terms of area, performance, power characteristics, or other characteristic(s).
REFERENCES:
patent: 6298472 (2001-10-01), Phillips et al.
patent: 6314553 (2001-11-01), Stevens et al.
patent: 6505339 (2003-01-01), Miller et al.
patent: 6745160 (2004-06-01), Ashar et al.
C2 Design Automation
Chiang Jack
Seed IP Law Group PLLC
Tat Binh
LandOfFree
Data path synthesis apparatus and method for optimizing a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data path synthesis apparatus and method for optimizing a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data path synthesis apparatus and method for optimizing a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3890747