Data path clock skew management in a dynamic power management en

Details Data path clock skew management in a dynamic power management en Data path clock skew management in a dynamic power management en

1998-04-01

2000-04-11

Heckler, Thomas M.

Electrical computers and digital processing systems: support

Computer power control

Power conservation

G06F 132

Patent

active

060498838

ABSTRACT:
A clock gating apparatus that is cost efficient and allows power conservation is presented. The clock gating apparatus is implemented to allow data paths, that are used to process data, to be enabled or disabled as desired while preventing the clock-skew problem. The clock gating apparatus includes a plurality of clock gating circuits, wherein one clock gating circuit is implemented for each data path. In a first embodiment, while all the data paths propagate data in a first direction and eventually merge together at a node, the clock gating circuits are connected together in a cascaded fashion to propagate a clock signal in a second direction opposite from the first direction. In a second embodiment, parallel data paths that are mutually exclusive of each other propagate data in a first direction and the clock gating circuits are connected together in a cascaded fashion to propagate a clock signal in a second direction opposite from the first direction.

REFERENCES:
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patent: 4999528 (1991-03-01), Keech
patent: 5585745 (1996-12-01), Simmons et al.
patent: 5615376 (1997-03-01), Ranganathan
patent: 5623646 (1997-04-01), Clarke
patent: 5740087 (1998-04-01), Smentek et al.

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