Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-02-25
2004-09-28
Decady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
06799290
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor testing and more particularly, to diagnostic test modes for testing data paths in isolation of a memory array.
2. Description of the Related Art
The evolution of sub-micron CMOS technology has steadily improved microprocessor speed. Quadrupling every three years, it has realized product chips with clock frequencies over 500 MHz and even an experimental chip with a 1 GHz clock frequency. It is highly desirable to have Dynamic Random Access Memories (DRAMs) not only with high density, but also with high bandwidth to narrow the bandwidth gap between microprocessors and DRAMs.
In general, high bandwidth DRAMs can be realized by pipelining a data path, for example, wave-pipelines or clocked-pipelines. Higher bandwidth can also be achieved by prefetching 2 or 4 bits per output data line. Pipelined prefetch architecture may be employed for DDR synchronous DRAMs, SinkLink DRAMS (SLDRAMs), and Rambus DRAMs (RDRAMs) with 200 MHz or beyond. This pipelined prefetch architecture, does however, require an accurate data path control for each pipeline stage and prefetch stage to make it work successfully, at the device level. Furthermore, as frequency increases, the communication between the memory device and a memory controller also requires more accurate data control at the system level. It is important to be able to verify the pipelined prefetch data path at the device level, and the memory's communication path with other devices while isolating the memory array.
Therefore, a need exists for test modes for testing data paths for semiconductor memories. A further need exists for data path test modes, which test the data path in isolation of a memory array. A still further need exists for calibration of a high speed memory device with a memory controller to provide accurate data control. The above needs should advantageously be provided without destruction of data stored in the memory array and while making dynamic calibration possible while an application is running.
SUMMARY OF THE INVENTION
A method for testing a data path for a semiconductor memory device, in accordance with the present invention, includes providing a semiconductor memory device including a plurality of stages in a data path, and transferring data into the data path. Components are disabled to isolate at least one stage of the plurality of stages such that data written to or read from the at least one stage is available at an output. The data at the output is preferably compared to expected data to confirm functionality.
A method for calibrating a data path for a memory device to provide communications between devices, in accordance with the present invention includes providing a semiconductor memory device including a plurality of stages in a data path and providing a memory controller for controlling memory operations of the memory device. Data is transferred into the data path, components are disabled to isolate at least one stage of the plurality of stages such that data written to or read from the at least one stage is available at an output. The data path is then calibrated to ensure proper communication between the memory controller and the memory device.
Another method for checking a data path for a semiconductor memory device, in accordance with the present invention, includes providing a semiconductor memory device including a plurality of stages in a data path, transferring data into the data path, maintaining the data on the plurality of stages, retrieving the data in the data path by disabling components at each stage to isolate each stage from the other stages to make the data available at an output and comparing the data at the output to expected data.
A method for testing a data path for a semiconductor memory device, in accordance with the present invention, includes the steps of providing a semiconductor memory device including a plurality of stages in a data path, transferring data into the data path, maintaining the data on the plurality of stages, and retrieving the data in the data path by disabling components at each stage to isolate each stage from the other stages to make the data available at an output. The step of retrieving includes the steps of disabling multiplexers to isolate a spine read write driver bus (SRWD) stage in the data path, retrieving the data at the SRWD stage, disabling multiplexers to isolate a quadrand read write driver bus (QRWD) stage in the data path, retrieving the data at the QRWD stage, disabling a column switch in the data path and retrieving the data from the MDQ's. The step of comparing the data at the output of each stage to expected data for that stage is also included.
In other methods one stage may include SRWD's and the step of disabling components may include the step of disabling multiplexers to isolate the one stage. One stage may include QRWD's and the step of disabling components may include the step of disabling multiplexers to isolate the one stage. One stage may include MDQ's and the step of disabling components may include the step of disabling a column switch to isolate an MDQ from a bitline. The at least one stage may include bitlines and the step of disabling components to isolate at least one stage may include the step of disabling a wordline to isolate a bitline. A calibration protocol may be provided which includes dynamically calibrating the data path. This protocol may provide communication between devices while running an application.
In still other methods, the data path may include sense amplifiers and the step of reading data directly from the sense amplifiers to test the data path may be included. The output may include a data line (DQ) pin. The method may include the step of calibrating the data path to set up for communications with other devices. The calibration may be performed by dynamically while running an application. The output may include a latch circuit. The output may be retrieved from a capacitive load. The data path may include sense amplifiers and the step of reading data directly from the sense amplifiers to test the data path may be included. One stage of the plurality of stages may include bitlines and the method may include the steps of disabling a wordline to isolate a bitline (and a memory cell).
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EPO Search Report.
Hanson David Russell
Kirihata Toshiaki
Mueller Gerhard
Chase Shelly A
De'cady Albert
Infineon Technologies North America Corp
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