Data path architecture and arbitration scheme for providing acce

Details Data path architecture and arbitration scheme for providing acce Data path architecture and arbitration scheme for providing acce

1995-12-01

1999-11-09

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

711 1, 711 5, 711127, 711147, 711151, 711168, 711169, 710112, 710113, 710118, 712 10, 370351, 370352, 370353, 370354, 370355, 370356, 370357, 370498, 36518902, 36523002, 36523003, 36523004, G06F 1314

Patent

active

059833270

ABSTRACT:
A system interconnect architecture and associated arbitration scheme that provides for the interleaving of multiple accesses to a shared system resource by multiple components on a data block by data block basis. According to one embodiment, an access request is granted "immediately" upon receipt such that the effective access latency between an access request and the transfer of a first data block (e.g. a byte. a word, a long word, and a double long word as determined by the width or throughput of the data path) for the access is the minimum access latency to the shared system resource. If a second access request is received while a first access is being performed, the second access request is granted immediately, and the first and second access are thereafter interleaved such that data blocks of the accesses are alternately transferred by the system interconnect.

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