Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Patent
1998-02-23
2000-08-15
Sheikh, Ayaz R.
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
710116, 710244, 370462, G06F 1300
Patent
active
061050954
ABSTRACT:
A data processing system (20) schedules the allocation of a common bus (26), used by multiple service requesters (32). The system (20) creates a plurality of service request levels (44) and assigns each service requester (32) to one of the plurality of request levels (44). Services of the common bus (26) are provided to all service requesters (32) assigned to a first service request level (44) for each instance of providing service to one of the service requesters (32) assigned to a second service request level (44). The method then again provides services of the common bus (26) to all service requesters (32) assigned to the first service request level (44) for a single instance of providing service to one of the second level requesters (32).
REFERENCES:
patent: 4979100 (1990-12-01), Makris et al.
patent: 5265257 (1993-11-01), Simcoe et al.
patent: 5440698 (1995-08-01), Sindhu et al.
patent: 5644733 (1997-07-01), Kalish et al.
patent: 5892766 (1999-04-01), Wicki et al.
patent: 5949789 (1999-09-01), Davis et al.
Lang Gary James
Miller Karl Eric
Gorrie Gregory J.
Lefkowitz Sumati
Motorola Inc.
Sheikh Ayaz R.
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