Data-packet fifo buffer system with end-of-packet flags

Details Data-packet fifo buffer system with end-of-packet flags Data-packet fifo buffer system with end-of-packet flags

1996-11-25

1999-01-12

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

395872, G06F 1200

Patent

active

058601198

ABSTRACT:
A packet-data FIFO buffer system comprises a FIFO buffer with a series of FIFO memory locations. Each FIFO memory location includes a data section for storing a packet data word and a flag section for storing an indication of whether or not the associated data section includes the last word of a packet. The FIFO buffer capacity is not limited to the number of maximum length packets it can hold; instead, a greater number of small packets can be stored. This increases the effectiveness of available FIFO memory and minimizes communication delays along the channels serviced by the FIFO. The FIFO design is simple and fairly self contained so that minimal external logic and control is required. In addition, an indication of the presence or absence of a complete data packet in the FIFO buffer can be easily obtained by logically adding (ORing) the contents of the flag sections.

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Flectcher, William J., An Engineering Approach to Digital Design, Prentice-Hall, Inc., Englewood Cliffs, NJ, 1980, pp. 418-421.
82930A Unviersal Serial Bus Microcontroller User's Manual, pp. 7-1-7-20. (No publication date or copyright date).
"Cypress Data Book: Memories, DataCom, FCT Logic, PC Products", Cypress Semiconductor Corp., San Jose, CA, 1-395DBOOK 8000, pp. 5-36 and 5-37, May 1995.

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