Data packet arithmetic logic devices and methods

Details Data packet arithmetic logic devices and methods Data packet arithmetic logic devices and methods

2006-11-21

2006-11-21

Treat, William M. (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

C708S670000

Reexamination Certificate

active

07139900

ABSTRACT:
New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disclosed. Also, a new dedicated SMAD logic device that performs a single instruction multiple data add (SMAD) operation in about one to two clock cycles is disclosed.

REFERENCES:
patent: 5838960 (1998-11-01), Harriman, Jr.
patent: 6047304 (2000-04-01), Ladwig et al.
patent: 0 395 348 (1990-10-01), None
Wagner J., Leupers R.; “C Compiler Design for a Network Processor” IEEE Transactions on Computer-Aided Design of Integrated Circutis and Systems, vol. 20, No. 11, Nov. 2001, pp. 1302-1308.

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