Data outputting circuit for semiconductor memory device

Details Data outputting circuit for semiconductor memory device Data outputting circuit for semiconductor memory device

1995-11-27

1997-05-20

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

36518911, 365207, G11C 700

Patent

active

056318650

ABSTRACT:
A semiconductor memory device includes a sense amplifier and a load circuit which are connected to a pair of data buses through which cell data is read. The sense amplifier produces an output data signal in accordance with voltage potentials of transfer signals on the data buses. During data reading operation of the memory device, the sense amplifier is enabled and the transfer signals on the data buses have a different voltage potential level from each other. The load circuit sets the data buses at a predetermined reset voltage potential in a stand by state of the data reading operation. The reset voltage potential is intermediate of the voltage potential levels of the data buses when the sense amplifier is enabled.

REFERENCES:
patent: 4733112 (1988-03-01), Yamaguchi

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