Data output timing in response to read command based on...

Details Data output timing in response to read command based on... Data output timing in response to read command based on...

2008-06-30

2011-11-01

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S230080, C365S230090, C365S233110, C327S293000, C327S294000

Reexamination Certificate

active

08050119

ABSTRACT:
A semiconductor memory device can output data according to a predetermined data output timing, in spite of a high frequency of system clock, even when a delay locked loop is disabled. The semiconductor memory device includes a delay locked loop configured to perform a delay locking operation on an internal clock to output delay locked clock, and a data output control unit configured to determine a data output timing, according to whether the delay locked loop is enabled or disabled, in response to a read command.

REFERENCES:
patent: 7542358 (2009-06-01), Jang
patent: 2001/0047464 (2001-11-01), Shinozaki
patent: 2008/0008283 (2008-01-01), Lee
patent: 2008/0056057 (2008-03-01), Kim et al.
patent: 2008/0079469 (2008-04-01), Cho
patent: 2008/0157836 (2008-07-01), Cho
patent: 2009/0116314 (2009-05-01), Byun
patent: 1020010066128 (2001-07-01), None
Notice of Preliminary Rejection issued from Korean Intellectual property Office on Dec. 22, 2008 with an English translation.

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