Data output circuit with improved overvoltage/surge protection

Electronic digital logic circuitry – Interface – Current driving

Reexamination Certificate

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Details

C326S087000

Reexamination Certificate

active

11090795

ABSTRACT:
A data output circuit is composed of first and second differential MOS transistors, first and second cascade MOS transistors, first and second outputs, and first and second resistor elements. The first and second differential MOS transistors receive first and second input voltages on the gates, respectively, sources of the differential MOS transistors being commonly connected. The first cascade MOS transistor is connected between the first differential MOS transistor and the first output, and the second cascade MOS transistor is connected between the second differential MOS transistor and the second output, gates of the first and second cascade MOS transistors being commonly connected. The first transistor element is connected between a ground line and the commonly connected gates, and the second transistor element is connected between a power supply line and the commonly connected gates.

REFERENCES:
patent: 5319259 (1994-06-01), Merrill
patent: 5589785 (1996-12-01), Garavan
patent: 6377121 (2002-04-01), Giduturi
patent: 6472908 (2002-10-01), Smetana
patent: 6522174 (2003-02-01), Martin et al.
patent: 6670830 (2003-12-01), Usami et al.
patent: 2002/0057017 (2002-05-01), Chan
patent: 2002/0149395 (2002-10-01), Martin et al.
patent: 08-6676 (1996-01-01), None
European Search Report dated Sep. 1, 2005.

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