Data output buffer with latch up prevention

Electronic digital logic circuitry – Interface – Current driving

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Details

327534, H03K 190175, H03K 19094

Patent

active

055460208

ABSTRACT:
A data output buffer comprising a pull-up transistor having an N type-well, the pull-up transistor transferring a supply voltage from a supply voltage source to an output line in response to a logic state of data from an input line, a first PMOS transistor for switching the supply voltage from the supply voltage source to the N type-well of the pull-up transistor in response to a voltage on the output line, and a second PMOS transistor for feeding the voltage on the output line back to the N type-well of the pull-up transistor when the voltage on the output line is higher than the supply voltage from the supply voltage source. According to the present invention, the voltage on the output line can be prevented from being latched up to the supply voltage source when it is higher than the supply voltage from the supply voltage source. Therefore, the data output buffer has an enhanced operation speed and a minimized occupying area in a semiconductor integrated circuit device.

REFERENCES:
patent: 5041894 (1991-08-01), Reczek et al.
patent: 5381056 (1995-01-01), Murphy
patent: 5381061 (1995-01-01), Davis
patent: 5396128 (1995-03-01), Dunning et al.
patent: 5434526 (1995-07-01), Tanigashira et al.

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