Data output buffer using a junction field effect transistor

Details Data output buffer using a junction field effect transistor Data output buffer using a junction field effect transistor

1992-03-16

1993-06-01

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307473, 307263, H03K 19094

Patent

active

052162940

ABSTRACT:
A data output buffer for use in a semiconductor memory with a junction-field-effect-transistor. The data output buffer has a N-channel MOSFET TN1 with its gate connected to terminal 10 for receiving data input DH from a logic circuit LC, a drain connected to power supply voltage V.sub.cc and a source connected to an output terminal 14. A N-channel MOSFET TN2 has a drain connected to the source of transistor TN1 and an output terminal 14, a source connected to a reference potential (e.g., a local ground) and a gate connected to the output of a CMOS inverter 20. A JFET JT has a drain connected to the power supply voltage Vcc, a source connected to the source of the P-channel MOSFET TP1 and a gate connected to a negative voltage V.sub.BB. A drain of the P-channel MOSFET TP1 is connected to terminal 16. A N-channel MOSFET TN3 has a drain connected to the drain of transistor TP1 via terminal 16 and a source connected to a reference potential (e.g., a local ground). The gates of transistors TP1 and TN3 are commonly connected to terminal 12 to receive output data DL from the logic circuit LC.

REFERENCES:
patent: 4477919 (1984-10-01), Borras et al.
patent: 4549101 (1985-10-01), Sood
patent: 4567378 (1986-01-01), Raver
patent: 4604731 (1986-08-01), Konishi
patent: 4779013 (1988-10-01), Tanaka

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