Data output buffer for multiple power supplies

Details Data output buffer for multiple power supplies Data output buffer for multiple power supplies

1996-08-19

1998-08-11

Santamauro, Jon

Electronic digital logic circuitry

Interface

Current driving

326 17, 326 27, H03K 190185, H03K 19094

Patent

active

057932263

ABSTRACT:
A data output buffer circuit for a semiconductor memory device operates with two separate power supplies and prevents malfunctions caused by the sequence in which the power supplies are energized. At lease one discharge transistor is used to remove charge from the gate of one or more NMOS push-pull transistors in an output buffer which can be floating in a charged state if one of the power supplies is energized before the other. In one embodiment, the gates of two discharge transistors are cross-coupled to the gates of the push-pull transistors to assure that at least one of the push-pull transistors are turned off. In an alternative embodiment, one or more discharge transistors are connected to the gates of at least one push-pull transistor and are controlled by a pulse generator that generates a pulse signal in response to variations in the voltage of the power supply for the push-pull transistors. In another alternative embodiment, the push-pull buffer includes a PMOS push transistor and an NMOS pull transistor. An inverter, which is powered by the same power supply as the push-pull buffer, drives the gate of the PMOS transistor. Two discharge transistors are connected to the gates of the push-pull transistors, and the gates of the two discharge transistors are cross-coupled to the gate of the NMOS pull transistor and the input of the inverter to assure that at least one of the push-pull transistors are turned off.

REFERENCES:
patent: 5124579 (1992-06-01), Naghshineh
patent: 5369316 (1994-11-01), Chen et al.
patent: 5391940 (1995-02-01), Linn
patent: 5430391 (1995-07-01), Fujimoto et al.
patent: 5559452 (1996-09-01), Saito
patent: 5604453 (1997-02-01), Pedersen

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