Data output buffer circuit for byte-wide memory

Details Data output buffer circuit for byte-wide memory Data output buffer circuit for byte-wide memory

1989-03-31

1990-11-20

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307450, 307451, 307570, 307263, H03K 1716, H03K 19017, H03K 19094

Patent

active

049721003

ABSTRACT:
An output buffer circuit for a byte wide memory is disclosed, including a circuit for delaying the falling or rising time of the gate voltage of a pull-up transistor of an output driver, located between a p-channel transistor and an n-channel transistor of the pull-up inverter; and a circuit for delaying the rising time of the gate voltage of a pull-down transistor of the output driver, located between a p-channel transistor and an n-channel transistor of the pull-down inverter. The disclosed delay circuits may include a depletion transistor having a gate and a source connected to each other. Through the provision of such delay mechanisms, the noise generations in both the power lines and the ground lines are reduced.

REFERENCES:
patent: 4816705 (1989-03-01), Ohba et al.

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