Data output buffer

Details Data output buffer Data output buffer

2000-01-14

2002-08-27

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

06442716

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a buffer and, more particularly, to a data output buffer of a semiconductor integrated circuit.
2. Background of the Related Art
Breakdowns and errors in operation of a semiconductor integrated circuit result from defects. Such defects of the semiconductor integrated circuit are caused by breakdowns during the use of the circuit as well as errors in the fabrication process.
The probability of defects in the semiconductor integrated circuit is called “failure rate”. The failure rate may be divided into three categories, infant mortality, useful life time and wear-out time.
The failure rate in the infant mortality results from breakdowns that are not detected in the test process, but exist in the integrated circuit, or defects that cause breakdowns. Most of the breakdowns develop from the initial defects in the useful life time of the integrated circuit. Usually, a test to detect the initial failure is carried out in the fabrication process of the integrated circuit. Such a test is called a “burn-in test”.
The burn-in test refers to a method of checking the presence of breakdowns by operating the integrated circuit under the conditions of high supply voltage and high temperature for a long time and then performing an examination for the performance of the integrated circuit. The conditions in the burn-in test mode are varied depending on the type of the product. If the regulated supply voltage is 5 volts, the burn-in test of a semiconductor memory, for example, imposes stress upon the semiconductor memory by performing write and read operations at a high voltage of 8 volts and at a temperature of about 100° C. for 24 hours or so.
Usually, the burn-in test is carried out for a plurality of chips at once to shorten the time for test of the semiconductor integrated circuit. The burn-in test is also performed for a plurality of chips in a simultaneous manner. To test plural chips at one time, the chips are connected in common to a data output pad and the burn-in test is performed. A semiconductor integrated circuit including a semiconductor memory is usually designed to output internally generated signals outwardly via a data output buffer. An output of the data output buffer is transferred to the data output pad.
FIG. 1
is a circuit diagram showing a related art data output buffer. As shown in
FIG. 1
, two inverter circuits
104
and
108
invert an output enable signal OE and a data signal D
OUT
, respectively, which are then input to a NOR gate
102
. The output enable signal OE and the inverted data signal D
OUT
are input to a NAND gate
106
. An output driving section is made up of a PMOS transistor
110
, which operates as a pull-up device, and an NMOS transistor
112
, which operates a pull-down device. The PMOS transistor
110
and the NMOS transistor
112
are connected in series between supply voltage V
DD
and ground line V
SS
.
The output of the NOR gate
102
is inverted by an inverter circuit
114
and applied to the gate of the PMOS transistor
110
. The output of the NAND gate
106
is inverted by an inverter circuit
116
and applied to the gate of the NMOS transistor
112
. An output line
118
, which is connected in common to the drains of the PMOS transistor
110
and the NMOS transistor
112
, is connected to a data output pad
120
.
If the output enable signal OE is set to “0” (i.e., low logic level), then the output driving section is in a floating state regardless of the logic value of the data signal D
OUT
. With the output signal OE at the low logic level, the output of the NOR gate
102
is 0, and the output of the NAND gate
106
is 1 (at a high logic level). The output of the NOR gate
102
, which is 0, is inverted to 1 (HIGH) turning the PMOS transistor
110
off. The output of the NAND gate
106
, which is 1, is inverted to 0 (LOW) turning the NMOS transistor
112
off.
If the output enable signal OE is set to 1, then the output driving section is pulled up or pulled down depending on the logic value of the data signal D
OUT
. If the output enable signal OE is 1, the outputs of the NOR gate
102
and the NAND gate
106
have the same logic value as the data signal D
OUT
. Accordingly, pull-up signal PU and pull-down signal PD output by the two inverter circuits
114
and
116
, respectively, in this case have the logic value opposite to the data signal D
OUT
.
If the output enable signal OE is set to 1 with the data signal D
OUT
being 1, the pull-up signal PU is 0 and the PMOS transistor
110
is on. At the same time, the pull-down signal PD is also 0 and the NMOS transistor
112
is off. Accordingly, the output line
118
is pulled up to the supply voltage to transfer output data signal DQ, which is 1, to the data output pad
120
.
If the output enable signal OE is set to 1 with the data signal D
OUT
being 0, the pull-up signal PU is
1
and the PMOS transistor
110
is off. At this time, the pull-down signal PD is also 1 and the NMOS transistor
112
is on. Thus, the output line
118
is pulled down to the ground level V
SS
to transfer the output data signal DQ, which is set to 0, to the data output pad
120
.
Such an operational characteristic of the related art data output buffer is illustrated in the timing diagram shown in FIG.
2
. As shown in
FIG. 2
, the output of the output data signal DQ conducts only while the output enable signal OE is 1.
As described above, the related art data output buffer has various disadvantages. In the related art data output buffer, shown in
FIG. 1
, the PMOS transistor
110
and the NMOS transistor
112
, which constitute the output driving section, have a high current driving capacity relative to the MOS transistors of the other circuits. The high current driving capability is required because the data output buffer is required not only to be at a logic level in accord to that of the external device, but also to drive a load of very high capacity at high speed. Thus, in the burn-in test mode in which a supply voltage much higher than the regulated voltage is applied, an excessive current flows across the output driving section of a data output buffer that has the high current driving capacity. Further, in case of a simultaneous test for multiple chips, it is difficult to perform a stable burn-in test because of such an excessive current flowing in the burn-in test board.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a data output buffer that substantially obviates one or more of the problems caused by disadvantages and limitations of the related art.
Another object of the present invention is to provide a data output buffer having an output driving section with multiple stages.
Another object of the present invention is to provide a data output buffer that has a reduced current flow in a burn-in mode.
Another object of the present invention is to divide the output driving section of a data output buffer into multiple stages and drive it in sequence.
Another object of the present invention is to provide a data output buffer with a first driving capability in a first mode and a reduced second driving capability in a second mode by sequentially using one of a plurality of stages in the second mode.
Another object of the present invention is to provide an output buffer for a plurality of chips that use a reduced current when concurrently driven in a burn-in-test.
To achieve at least the above objects of the present invention in a whole or in parts, a data output buffer includes an input circuit that receives a data signal and an output enable signal, wherein when the output enable signal is a prescribed value, first and second signals having logic values based on the data signal are output by the input circuit, a drive control circuit that receives a burn-in enable signal and a clock signal and activates a subset of a plurality of drive control signals, and a plurality of output driving circuits, each receiving the first and second signals and a corresponding one of the drive control signals, wh

Affiliated with

Also associated with

Rating

Data output buffer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data output buffer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data output buffer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2955911