Data ordering for cache data transfer

Details Data ordering for cache data transfer Data ordering for cache data transfer

2000-03-02

2001-11-20

DeCady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C710S035000

Reexamination Certificate

active

06321359

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to cache memory architectures and in particular to a data ordering which can be used in transfers from cache memory to increase the likelihood that the first words transferred will be useful.
2. Background Information
The speed with which a processor can access data is critical to its performance. At the same time, providing uniformly fast memory access can be cost prohibitive. To get around this problem, computer architectures have relied on a mix of fast, less dense, memory and slower bulk memory. In fact, many computer architectures have a multilevel memory architecture in which an attempt is made to find information in the fastest memory. If the information is not in that memory, a check is made at the next fastest memory. This process continues down through the memory hierarchy until the information sought is found. One critical component in such a memory hierarchy is a cache memory.
Cache memories rely on the principle of locality to attempt to increase the likelihood that a processor will find the information it is looking for in the cache memory. To do this, cache memories typically store contiguous blocks of data. In addition, the cache memory stores a tag which is compared to an address to determine whether the information the processor is seeking is present in the cache memory. Finally, the cache memory may contain status or error correcting codes (ECC). Cache memories are usually constructed from higher speed memory devices such as static random access memory (SRAM).
The typical cache memory transfers a cache line as a contiguous block of data, starting at the first word in the cache line and proceeding through to the last. This method of transferring cache lines does not take into account the fact that the processor may have no need for the first word in the cache line and that, therefore, it must wait a number of cycles until the word it is looking for is transferred.
What is needed is a method of ordering data transferred from a cache memory to a processor which increases the likelihood that useful data is transferred in the first transfer cycle.
SUMMARY OF THE INVENTION
The present invention is a system and method for ordering the transfer of data words within a cache line transfer. The cache memory receives an address from a processor and selects the cache line corresponding to the address. The cache memory then determines an order for transferring cache line data words from the selected cache line based on the likelihood that each data word in the order will be needed by the processor. The data words are then transferred to the processor in the desired order.


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